Virtual-Real Collaborated Split Learning via Model Partitioning in IRS-Assisted IoT Networks

TL;DR

This paper presents a novel split learning framework for IRS-assisted IoT networks that optimizes system delay through joint partitioning, IRS configuration, and resource allocation, leveraging digital twins.

Contribution

It introduces a delay-optimal split learning approach with joint optimization of layer partitioning, IRS phase shifts, and resource allocation in IRS-assisted IoT networks with digital twin integration.

Findings

Achieves up to 35% delay reduction compared to baselines

Effectively handles high user density and power constraints

Demonstrates significant delay improvements through extensive simulations

Abstract

This paper investigates a novel computation and communication co-design framework for large-scale split learning in intelligent reflecting surface (IRS)-assisted internet of things (IoT) networks integrated with digital twin (DT) technique. The considered system consists of a multi-antenna access point (AP), multiple heterogeneous user devices (UDs), and an deployed IRS to enhance both uplink and downlink transmission. The training process of a deep neural network is partitioned between devices and the AP, where a DT replica is activated to replace UDs with insufficient local computation capabilities. We formulate a delay-optimal split learning problem, which optimizes five key variables: layer partitioning points, DT assignment decisions, IRS phase shift matrix, AP downlink power allocation, and DT frequency adjustment, aiming to minimize the overall end-to-end delay under communication and computation. The proposed optimization problem is a highly coupled non-convex mixed-integer problem. Therefore, we solve using an alternating optimization approach combining closed-form updates, semidefinite relaxation (SDR), and low-complexity heuristics. Extensive simulations demonstrate that the proposed scheme significantly reduces training delay compared to conventional baselines and achieves up to 35\% delay improvement, especially under high UD density and stringent power constraints.