Evaluation of Wafer-Scale SOT-MRAM for Analog Crossbar Array Applications
Samuel Liu, Chen-Yu Hu, Ming-Yuan Song, Xinyu Bao, and Jean Anne C. Incorvia

TL;DR
This paper demonstrates wafer-scale SOT-MRAM devices with high performance and low noise, suitable for neural network accelerators, and explores their stochastic properties for binary neural network training and probabilistic modeling.
Contribution
The work fabricates and characterizes wafer-scale SOT-MRAM with enhanced properties and demonstrates their application in neural network training and probabilistic modeling.
Findings
Achieved 150% tunnel magnetoresistance ratio and 2 ns switching speed.
Attained 95% accuracy on MNIST with 2-bit quantization and noisy training.
Showed potential of stochastic SOT-MRAM for binary neural networks and probabilistic graph modeling.
Abstract
Analog crossbar arrays consisting of emerging memory devices can greatly alleviate the computational strain required by vector matrix multiplications for neural network applications. The ability to produce spin orbit torque-magnetic random-access memory (SOT-MRAM) at wafer-scale positions SOT-MRAM as a strong memory candidate. In this work, we fabricate and measure 300 mm-compatible SOT-MRAM with 150% tunnel magnetoresistance ratio, fast (2 ns) and low voltage (<1 V) operation, low energy dissipation (350 fJ), low write noise (0.1%), and low device-to-device variation of 10%. Through 2-bit quantization aware training and noisy training as mitigation techniques, the measured SOT-MRAM devices attain 95% on MNIST. The bi-stable anisotropy and stochastic switching of SOT-MRAM can additionally be leveraged for stochastic training of binary neural networks, able to reach ideal accuracy for a…
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