EthVault: A Secure and Resource-Conscious FPGA-Based Ethereum Cold Wallet

TL;DR

EthVault introduces a secure, resource-efficient FPGA-based Ethereum cold wallet with hardware-implemented cryptographic algorithms and resistance to side-channel attacks, enhancing security for digital assets.

Contribution

This work presents the first FPGA-based Ethereum cold wallet architecture with hardware cryptography and attack resistance, optimized for portability and resource efficiency.

Findings

ECC architecture resists side-channel and timing attacks

Design uses minimal FPGA resources

Implementation validated on Xilinx Zynq UltraScale+

Abstract

Cryptocurrency blockchain networks safeguard digital assets using cryptographic keys, with wallets playing a critical role in generating, storing, and managing these keys. Wallets, typically categorized as hot and cold, offer varying degrees of security and convenience. However, they are generally software-based applications running on microcontrollers. Consequently, they are vulnerable to malware and side-channel attacks, allowing perpetrators to extract private keys by targeting critical algorithms, such as ECC, which processes private keys to generate public keys and authorize transactions. To address these issues, this work presents EthVault, the first hardware architecture for an Ethereum hierarchically deterministic cold wallet, featuring hardware implementations of key algorithms for secure key generation. Also, an ECC architecture resilient to side-channel and timing attacks is proposed. Moreover, an architecture of the child key derivation function, a fundamental component of cryptocurrency wallets, is proposed. The design minimizes resource usage, meeting market demand for small, portable cryptocurrency wallets. FPGA implementation results validate the feasibility of the proposed approach. The ECC architecture exhibits uniform execution behavior across varying inputs, while the complete design utilizes only 27%, 7%, and 6% of LUTs, registers, and RAM blocks, respectively, on a Xilinx Zynq UltraScale+ FPGA