TL;DR
This paper introduces BBOPlace-Bench, a comprehensive benchmark for evaluating black-box optimization algorithms in chip placement, enabling fair comparison and fostering development of more effective solutions.
Contribution
It presents the first dedicated benchmark for BBO in chip placement, integrating multiple problem formulations and algorithms, and providing a flexible framework for testing and comparison.
Findings
Hyperparameter optimization outperforms sequence pair formulation.
Evolutionary algorithms outperform simulated annealing and Bayesian optimization.
EAs achieve state-of-the-art results in high-dimensional spaces.
Abstract
Chip placement is a vital stage in modern chip design as it has a substantial impact on the subsequent processes and the overall quality of the final chip. The use of black-box optimization (BBO) for chip placement has a history of several decades. However, early efforts were limited by immature problem formulations and inefficient algorithm designs. Recent progress has shown the effectiveness and efficiency of BBO for chip placement, proving its potential to achieve state-of-the-art results. Despite these advancements, the field lacks a unified, BBO-specific benchmark for thoroughly assessing various problem formulations and BBO algorithms. To fill this gap, we propose BBOPlace-Bench, the first benchmark designed specifically for evaluating and developing BBO algorithms for chip placement tasks. It integrates three problem formulations of BBO for chip placement, and offers a modular,…
Peer Reviews
Decision·ICLR 2025 Conference Withdrawn Submission
1. This paper decouples chip placement tasks into problem formulation, optimization algorithms, and problem evaluation. 2. This paper provides a comprehensive study of BBO for chip placement tasks.
1. This paper compares traditional black-box optimization (BBO) algorithms but lacks coverage of advanced BBO methods that leverage deep learning. Although the authors include some reinforcement learning (RL)-based methods, the omission of ChiPFormer, an advanced BBO method, is notable. Including ChiPFormer would be valuable, as it introduces deep learning-based advancements that are increasingly relevant to this field. Additionally, incorporating other advanced BBO methods using deep learning w
This paper presents a benchmark for chip placement that may have potential for industrial EDA applications.
(1) Chip placement is an industrial problem. It is not clear that whether experiment results on the benchmark are similar to those in the real industrial scenarios. It is mentioned in subsection 4.1 that “We empirically test methods in BBOPlace-Bench on ISPD 2005 and ICCAD 2015 benchmarks”. On one hand, the reasons for choosing the ISPD 2005 benchmark and ICCAD 2015 benchmarks should be better described. On the other hand, the empirical test may not reflect the real performance in the industrial
For those interested in chip placement, this paper could be a convenient place to see the performance of different algorithms directly compared using (presumably) popular benchmarks.
The comparison is billed as proposing a benchmark. This is confusing as the benchmarks are really existing benchmarks ISPD 2005 and ICCAD 2015. Beyond presenting the background and comparison results, the paper offers very little insight.
- The paper is very well-written. - The writing and illustrations are clear and help in understanding the motivation and solution.
- There is no comparison with analytical-based macro placement algorithms. In recent years, academia has proposed analytical-based macro placement algorithms. Additionally, there are algorithms for mixed-size placement that perform macro and standard cell placement simultaneously. Compared to RL-based methods, these algorithms are faster. The authors should include a comparison with analytical macro placement algorithms regarding performance and HPWL. This includes, but is not limited to: - Yu
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