RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN

TL;DR

RAMAN introduces a resource-efficient approximate posit-based MAC architecture with hardware-software co-design, significantly reducing area and power consumption while maintaining high accuracy for edge-AI applications.

Contribution

It proposes a novel approximate posit MAC architecture and a co-design framework that enhances hardware efficiency without substantially sacrificing AI model accuracy.

Findings

Achieves up to 46% LUT savings on FPGA

Reduces area by 35.66% and power by 31.28% on ASIC

Maintains 98.45% accuracy in digit recognition

Abstract

Edge-AI applications still face considerable challenges in enhancing computational efficiency in resource-constrained environments. This work presents RAMAN, a resource-efficient and approximate posit(8,2)-based Multiply-Accumulate (MAC) architecture designed to improve hardware efficiency within bandwidth limitations. The proposed REAP (Resource-Efficient Approximate Posit) MAC engine, which is at the core of RAMAN, uses approximation in the posit multiplier to achieve significant area and power reductions with an impact on accuracy. To support diverse AI workloads, this MAC unit is incorporated in a scalable Vector Execution Unit (VEU), which permits hardware reuse and parallelism among deep neural network layers. Furthermore, we propose an algorithm-hardware co-design framework incorporating approximation-aware training to evaluate the impact of hardware-level approximation on application-level performance. Empirical validation on FPGA and ASIC platforms shows that the proposed REAP MAC achieves up to 46% in LUT savings and 35.66% area, 31.28% power reduction, respectively, over the baseline Posit Dot-Product Unit (PDPU) design, while maintaining high accuracy (98.45%) for handwritten digit recognition. RAMAN demonstrates a promising trade-off between hardware efficiency and learning performance, making it suitable for next-generation edge intelligence.