Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis

TL;DR

Simopt-Power is a simulation-driven optimization framework that reduces FPGA dynamic power by selectively reconfiguring high-toggle paths based on simulation analysis, achieving significant power savings with minimal resource overhead.

Contribution

It introduces a novel method leveraging simulation metadata to identify and reconfigure high-toggle paths, improving power efficiency without major design changes.

Findings

Achieves ~9% power reduction on benchmark designs.

Increases resource usage by ~9% for arithmetic designs.

Demonstrates practical use of simulation data in FPGA optimization.

Abstract

Excessive switching activity is a primary contributor to dynamic power dissipation in modern FPGAs, where fine-grained configurability amplifies signal toggling and associated capacitance. Conventional low-power techniques -- gating, clock-domain partitioning, and placement-aware netlist rewrites - either require intrusive design changes or offer diminishing returns as device densities grow. In this work, we present Simopt-power, a simulator-driven optimisation framework that leverages simulation analysis to identify and selectively reconfigure high-toggle paths. By feeding activity profiles back into a lightweight transformation pass, Simopt-power judiciously inserts duplicate truth table logic using Shannon Decomposition principle and relocates critical nets, thereby attenuating unnecessary transitions without perturbing functional behaviour. We evaluated this framework on open-source RTLLM benchmark, with Simopt-power achieves an average switching-induced power reduction of ~9\% while incurring only ~9\% additional LUT-equivalent resources for arithmetic designs. These results demonstrate that coupling simulation insights with targeted optimisations can yield a reduced dynamic power, offering a practical path toward using simulation metadata in the FPGA-CAD flow.