Accelerating Electrostatics-based Global Placement with Enhanced FFT Computation

TL;DR

This paper introduces an accelerated FFT method, AccFFT, that significantly speeds up electrostatics-based global placement in VLSI design, leading to faster runtimes and improved placement quality.

Contribution

The paper presents a novel accelerated FFT technique, AccFFT, which enhances the efficiency of electrostatics-based placement algorithms in VLSI design.

Findings

5.78x faster FFT computation with AccFFT.

32% reduction in total runtime for placement algorithms.

1.0% improvement in wirelength after detailed placement.

Abstract

Global placement is essential for high-quality and efficient circuit placement for complex modern VLSI designs. Recent advancements, such as electrostatics-based analytic placement, have improved scalability and solution quality. This work demonstrates that using an accelerated FFT technique, AccFFT, for electric field computation significantly reduces runtime. Experimental results on standard benchmarks show significant improvements when incorporated into the ePlace-MS and Pplace-MS algorithms, e.g., a 5.78x speedup in FFT computation and a 32% total runtime improvement against ePlace-MS, with 1.0% reduction of scaled half-perimeter wirelength after detailed placement.