HHEML: Hybrid Homomorphic Encryption for Privacy-Preserving Machine Learning on Edge

TL;DR

This paper introduces a hardware-accelerated hybrid homomorphic encryption framework that significantly reduces latency and power consumption for privacy-preserving machine learning on edge devices, combining symmetric encryption with FHE.

Contribution

It presents the first end-to-end hardware-accelerated HHE architecture optimized for edge PPML, with microarchitectural enhancements and a scalable hardware-software co-design approach.

Findings

Over 50x reduction in client-side encryption latency

Nearly 2x increase in hardware throughput

Feasibility of low-power, hardware-accelerated HHE for edge deployment

Abstract

Privacy-preserving machine learning (PPML) is an emerging topic to handle secure machine learning inference over sensitive data in untrusted environments. Fully homomorphic encryption (FHE) enables computation directly on encrypted data on the server side, making it a promising approach for PPML. However, it introduces significant communication and computation overhead on the client side, making it impractical for edge devices. Hybrid homomorphic encryption (HHE) addresses this limitation by combining symmetric encryption (SE) with FHE to reduce the computational cost on the client side, and combining with an FHE-friendly SE can also lessen the processing overhead on the server side, making it a more balanced and efficient alternative. Our work proposes a hardware-accelerated HHE architecture built around a lightweight symmetric cipher optimized for FHE compatibility and implemented as a dedicated hardware accelerator. To the best of our knowledge, this is the first design to integrate an end-to-end HHE framework with hardware acceleration. Beyond this, we also present several microarchitectural optimizations to achieve higher performance and energy efficiency. The proposed work is integrated into a full PPML pipeline, enabling secure inference with significantly lower latency and power consumption than software implementations. Our contributions validate the feasibility of low-power, hardware- accelerated HHE for edge deployment and provide a hardware- software co-design methodology for building scalable, secure machine learning systems in resource-constrained environments. Experiments on a PYNQ-Z2 platform with the MNIST dataset show over a 50x reduction in client-side encryption latency and nearly a 2x gain in hardware throughput compared to existing FPGA-based HHE accelerators.