Impact of Switching Layer Architecture on Power Consumption in RRAM

TL;DR

This study shows that porous helical WOx architectures in RRAM devices enable a low-power operation regime with significantly reduced voltages and currents, leading to improved memory performance and potential for flexible electronics.

Contribution

The paper introduces porous helical WOx structures as a novel architecture that achieves low-power operation and enhanced memory window in RRAM devices.

Findings

Reproducible operation at 500 uA with 60% lower RESET voltage

Switching currents decrease by 68-75% in helical devices

Power consumption drops by approximately 83-89% in the low-power regime

Abstract

This work demonstrates that porous helical WOx architectures enable a distinct low-power regime for planar ITO/WOx/ITO resistive random-access devices. While thin film and helical devices behave similarly at a 5 mA compliance, only helical devices sustain reproducible operation at 500 uA, where RESET voltages reduce by ~60%, switching currents decrease by 68-75%, and SET/RESET power drops by ~89% and ~83%. With helical devices operating at 500 uA, the memory window expands 400-600% due to selective suppression of high-resistive-state leakage, yielding both lower-power and improved read margin in a regime inaccessible to thin film devices. These results highlight geometry-driven field enhancement and confinement as practical design principles for low-power, high-margin resistive memories and point toward opportunities in transparent, flexible, and high-surface-area material systems.