Synthesizing an Optimal Spin Qubit Shuttling Bus Architecture for the Surface Code

TL;DR

This paper introduces a novel optimized shuttling bus architecture for the surface code in spin qubit quantum computers, enabling scalable error correction with low logical error rates.

Contribution

It presents a new methodology called Quantum Reverse Mapping and formulates a mixed-integer optimization model for designing efficient shuttling architectures.

Findings

Achieves logical error rates as low as 2×10^{-10} at code distance 21.

Provides a scalable heuristic matching optimal solutions with linear complexity.

Demonstrates the architecture's feasibility through quantum simulations under realistic noise models.

Abstract

As quantum computers scale toward millions of physical qubits, it becomes essential to robustly encode individual logical qubits to ensure fault tolerance under realistic noise. A high-quality foundational encoding allows future compilation techniques and heuristics to build on optimal or near-optimal layouts, improving scalability and error resilience. In this work, we synthesize a one-dimensional shuttling bus architecture for the rotated surface code, leveraging coherent spin-qubit shuttling, following a novel methodology we name Quantum Reverse Mapping. We formulate a mixed-integer optimization model that yields optimal solutions with relatively low execution time for small code distances, and propose a scalable heuristic that matches optimal results while maintaining linear computational complexity. We evaluate the synthesized architecture using architectural metrics, such as shuttling distance and cycle time, and full quantum simulations under realistic noise models, showing that the proposed design can sustain logical error rates as low as $2\times 10^{-10}$ per round at code distance 21, showcasing its feasibility for scalable quantum error correction in spin-based quantum processors.