ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine

TL;DR

This paper introduces a resource-efficient, low-latency cortical neural acceleration engine using a novel FPGA-based neuron model, achieving significant improvements in speed, resource usage, and accuracy for edge AI applications.

Contribution

The paper presents a new FPGA implementation of a Hodgkin-Huxley neuron model with a modular CORDIC architecture and a novel parallelism technique, enabling efficient neural network acceleration.

Findings

24.5% LUT reduction and 35.2% speed improvement over state-of-the-art designs

2.85x higher throughput (12.69 GOPS) than equivalent DNN engine

Only 0.35% accuracy drop on MNIST dataset

Abstract

We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC based Hodgkin-Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN approaches, the proposed neuron leverages modular and performance-optimised CORDIC stages with a latency-area trade-off. We introduce a novel Constraint-Aware Modular Parallelism (CAMP) with Precision & Stability handling to leverage maximum speedup and utilisation of hardware through hardware software co-design. The FPGA implementation of the RCHH neuron shows 24.5% LUT reduction and 35.2% improved speed, compared to SoTA designs, with 70% better normalised root mean square error (NRMSE). Furthermore, the CNP exhibits 2.85x higher throughput (12.69 GOPS) than a functionally equivalent CORDIC-based DNN engine, with only a 0.35% accuracy drop relative to the DNN counterpart on the MNIST dataset. The overall results indicate that the design shows biologically accurate, low-resource spiking neural network implementations for resource-constrained edge AI applications. The reproducibility codes are publicly available at https://github.com/mukullokhande99/CNP RCHH, facilitating rapid integration and further development by researchers.