SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

TL;DR

SmaRTLy introduces a novel RTL optimization method that leverages logic inferencing and structural rebuilding to significantly reduce gate count in multiplexer-heavy designs, outperforming traditional tools like Yosys.

Contribution

It presents innovative strategies for removing redundant multiplexers and restructuring remaining ones, improving RTL optimization through logic inferencing and structural rebuilding.

Findings

Achieves 8.95% additional AIG area reduction on benchmarks.

Removes 47.2% more AIG area on industrial-scale benchmarks.

Demonstrates effectiveness of logic inferencing in RTL optimization.

Abstract

This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and traditional tools like Yosys optimize them by traversing the tree and monitoring control port values. However, this method does not fully exploit the intrinsic logical relationships among signals or the potential for structural optimization. To address these limitations, we develop innovative strategies to remove redundant multiplexer trees and restructure the remaining ones, significantly reducing the overall gate count. We evaluate smaRTLy on the IWLS-2005 and RISC-V benchmarks, achieving an additional 8.95% reduction in AIG area compared to Yosys. We also evaluate smaRTLy on an industrial benchmark in the scale of millions of gates, results show that smaRTLy can remove 47.2% more AIG area than Yosys. These results demonstrate the effectiveness of our logic inferencing and structural rebuilding techniques in enhancing the RTL optimization process, leading to more efficient hardware designs.