An Exact Branch and Bound Algorithm for the generalized Qubit Mapping Problem

TL;DR

This paper introduces an exact branch and bound algorithm for the generalized Qubit Mapping Problem, addressing limitations of existing layered approaches and demonstrating improved circuit compilation results.

Contribution

It presents a flexible, exact algorithm capable of solving various versions of the Qubit Mapping Problem, including those ignoring layering and gate timing constraints.

Findings

Ignoring layering can significantly improve circuit performance.

The algorithm finds proven optimal solutions for all problem variations.

Benchmark results show benefits of flexible QMP solutions.

Abstract

Quantum circuits are typically represented by a (ordered) sequence of gates over a set of virtual qubits. During compilation, the virtual qubits of the gates are assigned to the physical qubits of the underlying quantum hardware, a step often referred to as the qubit assignment problem. To ensure that the resulting circuit respects hardware connectivity constraints, additional SWAP gates are inserted as needed, which is known as the qubit routing problem. Together, they are called the Qubit Mapping Problem (QMP), which is known to be NP-hard. A very common way to deal with the complexity of the QMP is to partition the sequence of gates into a sequence of gate groups (or layers). However, this imposes a couple of important restrictions: (1) SWAP gates can only be added between pairs of consecutive groups, and (2) all the gates belonging to a certain group have to be executed (in parallel) in the same time slot. The first one prevents gates to be re-arranged optimally, while the second one imposes a time discretization that practically ignores gate execution time. While this clearly reduces the size of the feasible space, little is still known about how much is actually lost by imposing a fixed layering when looking at the minimization of either the number of SWAPs or the makespan of the compiled circuit. In this paper, we present a flexible branch and bound algorithm for a generalized version of the QMP that either considers or ignores the gate layering and the gate execution time. The algorithm can find find proven optimal solutions for all variations of the QMP, but also offers a great platform for different heuristic algorithms. We present results on several benchmark sets of small quantum circuits, and we show how ignoring the layering can significantly improve some key performance indicators of the compiled circuit.

Tables

Table 1. Table 1 : Gates used for circuit generation.

Abbrevation	Gate	Gate Duration
ECR	Echoed Cross Resonance	4
ID	Identity	1
RZ	$z$-Rotation	1
SX	Square Root	1
X	$x$-Rotation	1
SWAP	Swap Qubits	15

Table 2. Table 2 : Instances

Hardware graph	Num qubits	Depth parameter	Num instances total
Linear	4, 5, 6	10, 15, 20	900
Grid	4, 6	10, 15, 20	600
Y	4, 5, 6	10, 15, 20	900

Table 3. Table 3 : Relative mean deviation comparison for 4(a) - 4(c) and 5(d) - 5(f) .

Hardware Graph	Objective	$N$	$N^S$	$N^{=}$	$\mathrm{RMD}$	${\mathrm{RMD}}^{\ne }$
Linear	depth	$900$	$900$	$679$	$0.48\%$	$1.96\%$
	num SWAPs		$892$	$604$	$4.05\%$	$12.53\%$
Grid	depth	$600$	$595$	$554$	$0.09\%$	$1.26\%$
	num SWAPs		$530$	$430$	$3.92\%$	$20.75\%$
Y	depth	$900$	$815$	$152$	$6.38\%$	$7.85\%$
	num SWAPs		$811$	$59$	$30.79\%$	$33.21\%$

Table 4. Table 4 : HOP value mean

Hardware Graph	Objective	Non-Layered	Layered	Difference
Linear	Depth	$64.13\%$	$64.02\%$	$0.11\%$
	Swaps	$64.61\%$	$64.42\%$	$0.19\%$
Grid	Depth	$69.06\%$	$68.92\%$	$0.14\%$
	Swaps	$69.78\%$	$69.84\%$	$-0.06\%$
Y	Depth	$70.04\%$	$69.41\%$	$0.63\%$
	Swaps	$70.02\%$	$69.81\%$	$0.21\%$

Equations

$$\mathcal{C}=\left[\{g_1,d_1\},\{g_2,d_2\},\dots ,\{g_N,d_N\}\right],g_i=(p_i,q_i)\in G,p_i,q_i\in Q,p_i\ne q_i,d_i\ge 0,$$

$$T=\{T_P,T_U\}$$

$$n=(f_n,i_n,e_n)$$

$${\mathcal{C}}^q=[\{g_i,d_i\}:g_i=(p_i,q_i),q\in \{p_i,q_i\}],q\in Q$$

$${\mathcal{C}}^{q,i}=[\{g_j,d_j\}:\{g_j,d_j\}\in {\mathcal{C}}^q,j\ge i\}],q\in Q,i\in \{1,\dots ,N\}$$

$$\delta (i)=d_i+\mathrm{Max}(0,\{\delta (j)\forall j:\{g_i,d_i\}<\{g_j,d_j\}),i\in \{1,\dots ,N\}$$

$$\lambda (q,i)=\sum _{\{g_j,d_j\}\in {\mathcal{C}}^{q,i}}{d}_j,q\in Q,\{g_i,d_i\}\in {\mathcal{C}}^q$$

$$Q_n^U=\{q\in Q:{\mathcal{C}}^q\cap {\mathcal{C}}_n\ne \varnothing \}$$

$$\{g_{m_n^q},d_{m_n^q}\}=\mathrm{Min}({\mathcal{C}}^q\cap {\mathcal{C}}_n),q\in Q_n^U$$

$$h^Q(n)=\mathrm{Max}\left({\left\{D_n^Q(q)+\delta (m_n^q)\right\}}_{q\in Q_n^U}\bigcup {\left\{D_n^Q(q)\right\}}_{q\in Q\setminus Q_n^U}\right)$$

$$\begin{split}H_{n}(i,\pi,j)=\operatorname{Max}\Big{(}\big{\{}&D^{Q}_{n}(p_{i})+\lambda(p_{i},m^{p_{i}}_{n})-\lambda(p_{i},i)+(j-1)d^{S},\\ &D^{Q}_{n}(q_{i})+\lambda(q_{i},m^{q_{i}}_{n})-\lambda(q_{i},i)+(N_{\pi}-j-1)d^{S}\big{\}}\\ \bigcup\big{\{}&D_{n}(v^{k}_{\pi})+(j+1-k)d^{S}\big{\}}_{k\in\{2,\dots,j\}}\\ \bigcup\big{\{}&D_{n}(v^{k}_{\pi})+(k-j)d^{S}\big{\}}_{k\in\{j+1,\dots,N_{\pi}-1\}}\Big{)}\end{split}$$

$$h^G(n)=\mathrm{Max}\{\delta (i)+\mathrm{Min}\{H_n(i,\pi ,j):\pi \in \Pi (A_n(p_i),A_n(q_i)),j\in \{1,\dots ,N_{\pi }-1\}\}$$

$$h_D(n)=\mathrm{Max}\{h^Q(n),h^G(n)\}$$

$$h_S(n)=s_n+\mathrm{Max}\{d_{\mathcal{G}}(A_n(p_i),A_n(q_i))-1\}$$

$$h(n)=w_D{h}_D(n)+w_S{h}_S(n)$$

$$L(i)=\mathrm{Max}(0,\{1+L(j)\forall j:\{g_j,d_j\}<\{g_i,d_i\}),i\in \{1,\dots ,N\}.$$

$$\mathrm{RMD}=\frac{1}{N^S}\sum _i\frac{(y_i^L-y_i^{NL})}{y_i^L}$$

Full text

1 Introduction

A quantum algorithm can be viewed as applying a unitary evolution to a specified initial state and then taking measurements [15]. In the computational gate model of quantum computing, this evolution is represented by a sequence of quantum gates. Each gate implements a unitary operation on one or more qubits. Gates are usually taken from a universal set of (parameterized) gates, which enables the representation of any unitary evolution by choosing just gates from this set. To achieve universality, at least one multi-qubit gate is required because multi-qubit interactions are essential for generating entanglement.

In practice, a quantum computer supports only a fixed native gate set, which acts as the hardware-specific realization of a universal gate set. This native set usually includes several single-qubit gates and one two-qubit entangling gate. To execute an algorithm, the target unitary is compiled into a sequence of these native gates, producing a set of physically realizable instructions that can be implemented directly on the quantum device. Most hardware platforms use the controlled NOT (CX) gate as their fundamental two‐qubit operation.111Controlled‐phase gates (CZ) are also common. One has $(I\otimes\mathrm{H})\mathrm{CZ}(I\otimes\mathrm{H})=\mathrm{CX}$, where $\mathrm{H}$ denotes the Hadamard gate. However, there is an important limitation: the application of two‐qubit gates is only possible between a fixed set of connected pairs of physical qubits. For example, superconducting devices often exhibit linear, star [6], or heavy‐hex connectivity [10]. Although trapped‐ion systems can support all‐to‐all connectivity [5], these platforms usually remain small in qubit count before requiring the assembly of additional traps with limited connectivity.

Most of the quantum computers currently available are NISQ devices, which are inherently affected by noise and errors due to hardware imperfections. Analyzing the specific impact of this noise on the execution of quantum algorithms remains a significant challenge. However, it is clear that applying more quantum gates increases circuit depth, resulting in longer runtimes and greater exposure to noise. Therefore, a key objective is typically to either minimize the number of gates in a quantum circuit or to minimize its depth.

Generally, the qubit connectivity of a quantum computer can be modeled as an undirected graph $\mathcal{G}=(V,E)$, where $V$ represents the set of physical qubits and $E$ is the set of edges indicating which pairs of qubits are connected. Throughout this work, we distinguish between two types of qubits:

• •

Virtual qubits refer to the qubits defined in the mathematical formulation of a quantum algorithm and are to be interpreted as purely abstract constructs. For this reason, they are not limited by hardware connectivity.

• •

Physical qubits are the actual qubits a quantum computer is operating with. As such, they are subject to the limitations imposed by their specific hardware realization. One key limitation is qubit connectivity, which we model using the hardware graph $\mathcal{G}$. Another is the noise, which means that each qubit is affected by hardware-induced errors over time.

In short, virtual qubits are used in the design of quantum algorithms. In order to execute these algorithms on quantum hardware, two transformations are necessary.

Gate Decomposition. The quantum gates must be decomposed into the native gate set available on the quantum device. This part of the transformation is not the focus of this work. Typically, it can be realized straightforwardly, as relations between common gates are known. A common assumption (see, for example, [14]), is that such a conversion is given and the resulting set of gates consists of one-qubit gates and one two-qubit gate. In the following, we also presume (without loss of generality) that the two-qubit gate is a CX gate. 2. 2.

Qubit Mapping. This consists of two interconnected subproblems. The qubit assignment problem [20] assigns each virtual qubit to a physical qubit222When using quantum error correction for fault-tolerant quantum computing, each virtual qubit is represented by multiple physical qubits that form a logical qubit. We do not consider this generalization here.. The qubit routing problem [11] adds the necessary SWAP gates when the assignment does not satisfy the device’s connectivity. In fact, when $\mathcal{G}$ is not fully connected, it becomes highly probable that any such assignment would contain at least one two-qubit gate whose virtual qubits are assigned to physical qubits that are not adjacent in $\mathcal{G}$. In this case, one or more SWAP gates need to be inserted, each of which simply swaps the virtual qubits residing on two adjecent physical qubits (at the cost of adding three CX gates). While the use of additional SWAP gates allows an assignment to satisfy the connectivity of the specific hardware $\mathcal{G}$, it also increases the overall error rate of quantum computations. Finding a mapping (i.e., assignment plus routing) that minimize error rate is called the Qubit Mapping Problem (QMP). As the error rate is difficult to compute or embed in optimization algorithms, it is typically substituted by proxy objectives such as minimizing the number of SWAP gates or minimizes the depth of the circuit. This is the main focus of this work.

In general, QMP is NP‐complete [16, 3], so most practical quantum compilers treat assignment and routing separately. Many approaches (see, for example, the well-known SABRE algorithm [11]) start by choosing and fixing an initial assignment, and then insert SWAP gates as necessary. Note that any possible assignment admits a routing that makes the mapping feasible for the specific hardware, therefore iterative heuristic methods tend to perform well in practice (since infeasibility is not a big issue). Recent surveys such as [12], [9], and [4] discuss various heuristic and exact methods for QMP. In this work, we try to challenge some of the most common assumptions when defining the QMP and it is important to do so via proven optimal solutions. Therefore, our focus will be on exact methods.

The literature on exact methods is rather limited and mostly involves either specific topologies (see, for example, [13]) or specific aspects of the problem (see, for example, [2]). A notable exception is the recent work by Nannicini et al. [14], which provides a mixed‐integer binary formulation that solves QMP optimally for circuits up to 8 qubits. Wagner et al. [17] extend this by proposing a matheuristic that again treats the assignment and routing separately, achieving faster runtimes with comparable solution quality. However, both of these approaches (like many others) assume that gates are grouped into sa-called layers, which are sets of gates that can be executed in parallel and assuming that all gates within a layer have identical duration. Between layers, one may insert SWAP gates, but those cannot occur within a layer. This assumption typically generates non-optimal mappings, as one can see in the example of Figure 1. The same assumption is exploited in [18], where the authors choose a SAT solver to perform a mapping that minimizes the number of SWAP gates.

This assumption is instead dropped in [21], where the authors develop an $A^{*}$ algorithm to compile $SU(4)$ quantum circuits while again minimizing the number of SWAP gates. The layered-based approach was also dropped in [19], in this case with a focus on time-optimal mapping, which minimizes the depth of the circuit while taking into account the execution time of each gate. Here, the authors develop a branch-and-bound algorithm that shares many ideas with ours, but employs a time-indexed approach that we think imposes an unnecessary time-discretization on the problem.

In this paper, we develop a flexible branch-and-bound algorithm that can be used to find exact solutions to a generic qubit mapping problem, that is one in which one could decide to minimize number of swaps or depth (or both at the same time with different weight) while taking into account gate execution time and deciding to impose or relax the layering constraint. This framework provides proven optimal solutions, but it can also be used as a heuristic simply by pruning more aggressively branches of the branch-and-bound tree. For example, a beam-search behavior can be achieved by limiting the number to nodes at each depth.

This flexible framework allows us to study the performance impact of several assumptions, for example by comparing solutions that satisfy the layering constraint to solutions that allow SWAP gates to be interleaved arbitrarily between two‐qubit gates. In particular, we show that this relaxation can significantly reduce the resulting circuit depth.

The remainder of the paper is organized as follows. In Section 2, we formally define the QMP. Section 3 describes our branch and bound algorithm and Section 4 presents computational results comparing our methods to existing compilers. Finally, Section 5 concludes and outlines future work.

2 Problem definition

Let $Q=\{q_{1},\,q_{2},\,\dots,\,q_{n}\}$ be a set of virtual qubits and let $G\subseteq Q\times Q$ be the set of ordered pairs of virtual qubits on which two‐qubit gates act. Without loss of generality, we can represent a quantum circuit as a sequence

[TABLE]

where $g_{i}$ denotes a two‐qubit gate acting on the (ordered) pair of virtual qubits $(p_{i},q_{i})$ (although the order of $(p_{i},q_{i})$ can often be ignored, the ordering simplifies our notation), and $d_{i}$ is the duration (i.e., execution time) of gate $g_{i}$. As noted in [21], a circuit implicitly induces a partial ordering of gates. For example, consider the circuit $\mathcal{C}=[\{(1,2),2\},\{(3,4),3\},\{(4,1),1\}]$. This can be drawn simply as a classical circuit on virtual qubits (see Figure 2(a)) or as a directed graph of precedence relationships (see Figure 2(b)). In particular, Figure 2(b) displays the flow of information through the quantum circuit with a so-called precedence graph (which is commonly used in scheduling applications) and highlights the precedence relationships between pairs of gates. In this graph, an arc of length $l$ between two nodes indicates that the event associated to the target node can only start $l$ time units after the start of the event associated with the source node. In our case, the length of the arcs represent gate execution time. These times can then be used to track the total execution time of the compiled circuit and to determine the minimum time after which a gate can be executed. For example, if $g_{1}$ and $g_{2}$ are executed at the same time, then $g_{3}$ can be executed only after $\max(2,3)=3$ time units. Tracking execution time precisely can be important, as the execution time of a $CX$ gate is typically 10 times the one of a single-qubit gate, and a SWAP gate is 3 times longer (as it combines 3 $CX$ gates in series). Although this graph will not be mentioned explicitly, these precedence relationships will be exploited by the algorithm described in the next section to drastically reduce the search space and guarantee feasibility.

Given these considerations, one could in fact see the qubit mapping problem as a scheduling problem, one in which the gates need to be scheduled in a physical quantum hardware while satisfying the connectivity constraints and minimizing the total execution time. We can then introduce a formal definition for our interpretation of the qubit mapping problem.

Definition 1

Given a set of virtual qubits $Q$, a circuit $\mathcal{C}=[\{g_{1},d_{1}\},\dots,\{g_{N},d_{N}\}]$ as described in (1), and a hardware graph $\mathcal{G}=(V,E)$, the Qubit Mapping Problem (QMP)consists of finding a schedule $\mathcal{S}=[\{a_{1},t_{1}\},\dots,\{a_{M},t_{M}\}]$ such that each $a_{k}$, $k\in\{1,\dots,M\},\ M\geq N$, is an ordered assignment $(i,j)$, $i,j\in V$ of physical qubits, and $t_{k}$ is its scheduled time of execution $t_{k}\geq 0$. In other words, the schedule determines over which physical qubits a gate should be executed and at which time. Some $a_{k}$ are associated to the original gates $g_{1},\dots,g_{N}$ while others will be associated to the necessary SWAP gates. Such a schedule $\mathcal{S}$ is considered feasible if:

• •

(Assignment constraints) each assignment $(i,j)$ belongs to the set of edges $E$;

• •

(Routing constraints) the “flow” of virtual qubits through the hardware must satisfy all precedence relationships defined by the circuit $\mathcal{C}$, and whenever a gate $(p,q)$, $p,q\in Q$ is assigned to the physical qubits $(i,j)$, $i,j\in V$, then $i,j$ must “contain” the virtual qubits $p,q$ at the time of execution;

A feasible schedule is optimal when it minimizes the total execution time of the circuit.

Note that a schedule $\mathcal{S}$ implicitly determines the initial assignment of virtual qubits to physical qubits, simply by looking the at the virtual qubits of the first gate that is ever applied to those physical qubits. For example, if the first gate executed on the physical qubits $i=1,j=2$ of a certain hardware graph was operating on the virtual qubits $p=3,q=4$, then we determine the initial assignment to be $i\leftarrow p$ and $j\leftarrow q$.

2.1 An example of a feasible schedule

To highlight the role of the assignment and routing constraints, consider the circuit of Figure 2 and the linear hardware graph $1-2-3-4$. (note that if the hardware graph was a complete graph with at least 4 nodes, then the problem would become trivial). Then, consider the naïve schedule $\mathcal{S}_{1}=[\{(1,2),0\}_{g_{1}},\{(3,4),0\}_{g_{2}},\{(4,1),3\}_{g_{3}}]$ (here the subscript is simply used to indicate which gate a certain qubit assignment is associated with). This schedule clearly does not satisfy the hardware graph constraints, since the edge $(4,1)$ (or $(1,4)$) does not exist in the hardware graph. The schedule $\mathcal{S}_{2}=[\{(1,2),0\}_{g_{1}},\{(3,4),0\}_{g_{2}},\{(3,4),3\}_{g_{3}}]$ satisfies all hardware graph constraints, but does not satisfy the routing constraints as the physical qubits 3 and 4 do not contain the correct virtual qubits 1 and 4. Then, we can add a pair of swap gates $s_{1}=(1,2)$ and $s_{2}=(1,3)$ to first swap virtual qubit 1 with 2 and then again 1 and 3, so that virtual 1 resides on physical qubit 3 before the execution of gate $g_{3}$. Assuming each swap gate takes 6 time units, a feasible schedule would be $\mathcal{S}_{3}=[\{(1,2),0\}_{g_{1}},\{(3,4),0\}_{g_{2}},\{(1,2),2\}_{s_{1}},\{(2,3),8\}_{s_{2}},\{(3,4),14\}_{g_{3}}]$.

Note that this is far from being optimal. In fact, there exists a schedule that does not even require additional swap gates, that is $\mathcal{S}_{4}=[\{(2,1),0\}_{g_{1}},\{(4,1),0\}_{g_{2}},\{(2,3),3\}_{g_{3}}]$.

3 A branch and bound algorithm

To solve the QMP we consider an exact branch and bound algorithm as it offers great flexibility both in the modeling and in the search strategies. In fact, with this framework it is easy to switch between different objective functions or to heuristically limit the search space if needed. A typical branch and bound algorithm is a tree search algorithm that recursively breaks the original minimization problem in smaller subproblems until it can prove that either a certain subproblem is optimal or the original problem is infeasible. An iteration of the algorithm consists of the following steps:

Selection: Choose a subproblem from the list of open subproblems and remove it from the list. If the list is empty, terminate. 2. 2.

Bounding/Fathoming: Compute a lower bound for the selected subproblem. If the subproblem is infeasible or the lower bound is greater than the best known feasible solution, go to 1. 3. 3.

Branching/Expansion: If the solution of the subproblem is feasible for the original problem, update the best known feasible solution. Otherwise, split the subproblem in two or more (disjoint) subproblems and add them to the queue of open subproblems.

In the rest of the section, we describe in details how we perform all this steps. The algorithm explores state nodes, starting with a root node $n_{0}$ with no scheduled gates, and expanding leaf nodes by adding unscheduled circuit gates or SWAP gates. To avoid exploring redundant and sub-optimal branches in the search tree, we will only expand nodes that belong to a Pareto front of all nodes added so far. The relevant part of the search tree in the algorithm can be presented as

[TABLE]

where $T_{P}$ is the set of all Pareto front nodes in the search tree, while $T_{U}\subseteq T_{P}$ are the currently unexpanded nodes. The overall tree search algorithm is described in Algorithm 1.

A node $n\in T_{N}$ in the search tree different from the root node $n_{0}$ can be represented as

[TABLE]

where $f_{n}$ is the parent node of $n$, $i_{n}\in\{0,\dots,N\}$ is the index of the gate scheduled from $f_{n}$ to $n$, either a SWAP gate if $i_{n}=0$ or a circuit gate $\{g_{i_{n}},d_{i_{n}}\}\in\mathcal{C}$ if $i_{n}>0$, and $e_{n}=(v_{n},w_{n})\in E$ is the hardware position where the gate was applied. By parent node backtracking, the node $n$ implicitly defines the set $\mathcal{C}_{n}\subseteq\mathcal{C}$ of the problem circuit gates that have not been scheduled yet and the set $Q_{n}\subseteq Q$ of all virtual qubits with at least one scheduled gate in the parent chain up to $n$. The set $Q_{n}$ contains all qubits with at least one gate in $\mathcal{C}\setminus\mathcal{C}_{n}$, but may also contain additional qubits from scheduled SWAP gates.

Each node defines the assignment map $A_{n}:Q_{n}\rightarrow V$ mapping virtual qubits to their current hardware positions. The node expansions must ensure consistency and injectivity of the assignment map. When new qubits are added to $Q_{n}$, they must first be assigned to an unassigned hardware position in the parent node, while the rest of the assignment map must be the same as for the parent. The positions $v_{n}$ and $w_{n}$ must be the assigned positions of the virtual qubits the gate is applied for, and in the case of a SWAP gate the assignment map must swap the values for the two gate qubits.

The depth $D_{n}(v)$ is the earliest time after the execution of all gates on a hardware qubit $v\in V$. It will be the scheduled time of $g$ plus the duration of $g$ where $g$ is the last gate scheduled to be executed on an edge of $v$, or 0 if no such gate has been scheduled. Gates are scheduled as early as possible after the completion of the previous gates on any of the same hardware qubits. The map $D_{n}$ defines a depth map $D^{Q}_{n}$ on $Q$ where $D^{Q}_{n}(q)=D_{n}(A_{n}(q))$ for assigned qubits $q\in Q_{n}$, and $D^{Q}_{n}(q)=0$ for unassigned qubits.

3.1 Node expansion

When a node $n$ is expanded, the algorithm will try to add child nodes to $n$ by adding new gates to the schedule without getting in conflict with the existing assignment. Both problem circuit gates and SWAP gates may be added. A circuit gate $g_{i}\in\mathcal{C}_{n}$ can only be added if it is minimal, i.e. the first unscheduled gate for both of its qubits. The gate must be added to a hardware edge and the two virtual qubits must be assigned to the two nodes of the hardware edge so that a qubit $q\in Q_{n}$ is assigned to $A_{n}(q)$ and a qubit $q\in Q\setminus Q_{n}$ is assigned to a hardware node $v\notin A_{n}(Q_{n})$. A SWAP gate can be added to any hardware edge and will swap the assignment values in $A_{n}$ for the gates already assigned to any of the edge positions, though our implementation does not add SWAPs to edges where neither position has a virtual qubit assigned to it. The expansion algorithm is described in Algorithm 2.

The algorithm uses a lazy assignment; a virtual qubit node is not assigned to a hardware position before it is first assigned by a gate. In this way, the algorithm solves both the routing and the initial qubit assignment, which is built through parent backtracking in the solution.

3.2 The Pareto front

The tree search nodes can be grouped into equivalence classes according to their state. Two nodes $n_{1}$ and $n_{2}$ are equivalent if they have the same assignment of virtual qubits to the hardware positions, and the same set of unscheduled gates, i.e. $Q_{n_{1}}=Q_{n_{2}}$, $A_{n_{1}}=A_{n_{2}}$, and $\mathcal{C}_{n_{1}}=\mathcal{C}_{n_{2}}$. The Pareto front nodes $T_{P}$ are the nodes that are part of the Pareto front of minimal depth values for their states. So when we create a new node $n$ in the algorithm, it can be pruned if there is already a node $n^{\prime}\in T_{P}$ with the same state as $n$, and where $D_{n^{\prime}}$ is equal to or dominated by $D_{n}$. Otherwise $n$ will be added to $T_{P}$ and $T_{U}$, while other nodes that are no longer in the Pareto front will be removed from $T_{P}$ and $T_{U}$, as described in Algorithm 3.

3.3 Lower bound function

To help the algorithm search for an optimal solution to the qubit mapping problem, we use a measure $h(n)$ on the total execution time of the circuit for the best solution from $n$. The tree search algorithm uses this measure by always expanding a node from $T_{U}$ that minimizes $h(n)$. If $h(n)$ is always a lower bound, the search algorithm will be admissible and always return an optimal solution if solutions exist.

To help us define $h(n)$ as a lower bound, we need some utility measures on the circuit gates.

Definition 2

Given a set of virtual qubits $Q$ and a circuit $\mathcal{C}=[\{g_{1},d_{1}\},\dots,\{g_{N},d_{N}\}]$ as described in (1).

The set $\mathcal{C}^{q}$ is the set of all gates that apply to the qubit $q$.

[TABLE]

The set $\mathcal{C}^{q,i}$ is the set of all gates that apply to the qubit $q$ from $g_{i}$ or later.

[TABLE]

The minimal time $\delta(i)$ from the scheduled time of $g_{i}$ to the scheduled completion of the entire circuit is recursively given by

[TABLE]

where the relation $\{g_{i},d_{i}\}<\{g_{j},d_{j}\}$ expresses the partial ordering of the gates in the circuit.

The remaining execution time $\lambda(q,i)$ of gates that apply to the qubit $q$ from $g_{i}$ or later is given by

[TABLE]

From a node in the search tree, the depth of a qubit in a final solution cannot be smaller than its current depth plus the minimal time from the scheduled time of its first unplanned gate (if any) to the scheduled time of the entire circuit. This gives a first simple lower bound on the optimal solution depth from a node, which is the actual depth if the remaining gates were to be planned on a complete hardware graph.

Definition 3

Given a set of virtual qubits $Q$, a circuit $\mathcal{C}=[\{g_{1},d_{1}\},\dots,\{g_{N},d_{N}\}]$ as described in (1) and a node $n$ in the search tree.

The set $Q^{U}_{n}$ is the set of virtual cubits that still have unscheduled gates in $\mathcal{C}_{n}$

[TABLE]

For a virtual qubit $q$ with unscheduled gates, we define $m^{q}_{n}$ to be the index of the first such gate.

[TABLE]

The qubit based depth heuristic $h^{Q}$ on the node $n$ is defined by

[TABLE]

To improve this heuristic, we include an estimate on the possible delays from repositioning qubits of unscheduled gates. For two hardware qubits $v$ and $w$ we let $\Pi(v,w)$ be all minimal hardware paths $\pi=(v^{1}_{\pi},\dots,v^{N_{\pi}}_{\pi})$ where $v^{1}_{\pi}=v$, $v^{N_{\pi}}_{\pi}=w$ and $(v^{i}_{\pi},v^{i+1}_{\pi})\in E$ for all $i$. Minimality means no subset of hardware qubits can be removed from $\pi$ and still give a valid hardware path from $v$ to $w$.

If we try by SWAP operations to move the virtual qubit $p$ from position 1 to position $j$ on the hardware path $\pi$ before we execute the gate $g_{i}$ in $\mathcal{C}^{p}$, there are some lower bounds on how early the gate can be scheduled. One is based on the duration of the gates that must be applied on $p$ before $g_{i}$, this is $\lambda(p,m^{p}_{n})-\lambda(p,i)$ for the circuit gates plus $(j-1)d^{S}$ for the SWAP gates. The other is based on the depths $D_{n}(v^{k}_{\pi})$ of the hardware qubits that swap with $p$ for $k\in\{2,\dots,j\}$. A similar set of bounds exists for the virtual qubit $q$ to be moved from position $N_{\pi}$ to position $j+1$ on $\pi$. This gives the following scheduling bound for an unscheduled gate by moving its qubits to a specific path edge.

Definition 4

Given a set of virtual qubits $Q$, a circuit $\mathcal{C}$ as described in (1), a node $n$ as described in (3), an unscheduled gate $g_{i}=(p_{i},q_{i})$ such that $\{g_{i},d_{i}\}\in\mathcal{C}_{n}$, a path $\pi\in\Pi(A_{n}(p_{i}),A_{n}(q_{i}))$ and a position $j\in\{1,\dots,N_{\pi}-1\}$. Then we define

[TABLE]

which is a lower bound on how early $g_{i}$ can be scheduled by moving $p_{i}$ and $q_{i}$ along $\pi$ to the edge $(v^{j}_{\pi},v^{j+1}_{\pi})$.

By taking the minimum of $H_{n}(i,\pi,j)$ over all minimal paths $\pi$ between the hardware positions of $p_{i}$ to $q_{i}$, and all edge positions $j$ in the hardware graph, we get a lower bound on the scheduled start time of the gate $g_{i}$. By adding $\delta(i)$ we get the lower bound contribution from $g_{i}$ to the heuristic $h^{G}(n)$, which together with $h^{Q}(n)$ defines the heuristic $h(n)$ used in the tree search.

Definition 5

Given a set of virtual qubits $Q$, a circuit $\mathcal{C}=[\{g_{1},d_{1}\},\dots,\{g_{N},d_{N}\}]$ as described in (1) and a node $n$ as described in (3). The gate based depth heuristic $h^{G}$ on the node $n$ is defined by

[TABLE]

taken over all gates $g_{i}=(p_{i},q_{i})$ in $\mathcal{C}_{n}$ such that $p_{i},q_{i}\in Q_{n}$.

The function $h_{D}$ giving a lower bound for the depth of optimal solution from $n$ is defined by

[TABLE]

which is also our lower bound function $h$ used by the algorithm to select the next node to expand. Notice that to get $h^{G}$, it is sufficient to look at the gates that are the first unscheduled common gate of the two qubits they apply to, i.e. all $g_{i}=(p_{i},q_{i})$ where $\{g_{i},d_{i}\}=\operatorname{Min}(\mathcal{C}^{p_{i}}\cap\mathcal{C}^{q_{i}}\cap\mathcal{C}_{n})$.

3.4 Consider SWAP count in the objective

Instead of searching for a solution that minimizes the qubit depths, we can let the objective be to minimize the number of SWAP gates added to the solution, or a weighted combination of depth and SWAP gate count. The Pareto front value domain in the algorithm will must then be extended with an extra dimension for $s_{n}$, the number of scheduled SWAP gates.

As a lower bound $h_{S}$ for the total number of SWAPs in the final solution, we look for the unscheduled gate with longest distance between the current position of its qubits, and add the number of SWAPs needed to position the qubits next to each other. This gives

[TABLE]

taken over all gates $g_{i}=(p_{i},q_{i})$ in $\mathcal{C}_{n}$ such that $p_{i},q_{i}\in Q_{n}$, where $d_{\mathcal{G}}$ is the distance function on the hardware graph.

The combined lower bound function $h$ is updated to combine measures on depth and SWAPs by

[TABLE]

where $w_{D}$ and $w_{S}$ are the weights of the depth and number of SWAPs in the objective function.

3.5 Layering of gates

The algorithm also allows us to impose the layering constraints. In fact, with the following modification, the algorithm basically follows the same constraints described in [14].

Each gate $\{g_{i},d_{i}\}$ can be given a layer index $L(i)$, recursively defined by

[TABLE]

The gates with layer [math] are all gates that can be planned before any other gate, the gates with layer $1$ are the remaining gates that can be planned if all gates of layer [math] are planned, etc.

It is possible to run the algorithm in layering mode. This would imply that the node expansion in Algorithm 2 will not add any node that schedules a gate with layer $l$ before all gates with layer $l-1$ have been scheduled. If we run the search algorithm in layering mode, we may improve the execution time since the search tree is narrowed, but there is a risk that we can miss an optimal solution where a gate must be planned before one with a lower layer.

4 Computational results

We compare the layered to the non-layered approach by computing solutions for both methods with Algorithm 1 and comparing the results with metrics introduced in the following section. We use different hardware graphs to highlight the effect on the metrics used when there is a large difference in connectivity and centrality of the graph. Finally, we add noise to the results and compute the heavy output probability, a metric widely used in analysis of gate-based scheduling operations (see for example [7] and [1]). All implementations have been done in Python.

4.1 Instance generation and metrics

For each instance we create a randomly generated circuit, using the top five gates displayed in Table 1, which are derived from the IBM ibm_kyoto backend. To determine the timings, the gates were transpiled as single-gate circuits by Qiskit and their duration was measured. The gate durations of Table 1 are those measured timings, divided by $16$. Additionally we measured the time for a SWAP operation, which is needed for transpilation but not explicitly used for initial circuit generation and also divide it by $16$. Single-qubit gates are not scheduled explicitly by Algorithm 1, but contribute to the time of the two-qubit gate acting on the same qubit. To do this, we count each single-qubit gate up to the next two-qubit gate in the circuit and add their durations to the scheduling time of the latter. For simplicity, the last single-qubit gates in the circuit, if existing, are omitted when computing the circuit duration.

We compare the solutions of Algorithm 1 with layering on and off on three hardware graphs with a varying number of qubits, a Linear graph, a Grid graph and a Y graph, see Figure 3. Each hardware graph used has unique specifications regarding connectivity and centrality which will reflect in the solution quality.

We generate $100$ instances for each combination of number of qubits in the hardware graph and a depth parameter, which is used by Qiskit for random circuit generation. For generation we make use of the random_circuit() function provided by the qiskit.circuit.random module. The gates scheduled by Qiskit for the circuit generation are all available gates; we transpile the output circuit again on a complete hardware-graph with the backend used to achieve a circuit that only consists of the top five gates from Table 1. Through the equivalent conversion of gates, the depth of the circuit changes.

The instances are solved using a Python implementation of Algorithm 1, which is based on two objective functions: the number of SWAPs and the circuit depth, with the latter weighted by the durations listed in Table 1. For each objective we run Algorithm 1 two times, one time with layering being active and one time being inactive (non-layered). The solutions are then compared with three metrics; the depth, the number of SWAPs and additionally the (unweighted) depth, which is the makespan of the circuit w.r.t. the number of gates. Additionally we compare for both objectives the heavy output probability of the distributions of the solutions, which is the probability that a noisy repetition of an experiment hits its ideal significant solutions. More specifically, if $P$ is a distribution of a state vector of $n$ qubits and $\overline{p}$ is the median, then the heavy output is $H:=\{x\mid P(x)>\overline{p}\}$. Now let $\{q(x)\mid x\in\{0,1\}^{n}\}$ be the probabilities of a noisy experiment, then the heavy output probability is $\sum_{x:x\in H}q(x)$, i.e. the probability that the noisy experiment hits the heavy output.

We use the AerSimulator to compute Heavy Output Probability (HOP) for the benchmark circuits. For the ideal distribution we run the transpiled circuit using the statevector method. The noise model was generated with the same backend used to generate the circuits, i.e. the ibm_kyoto hardware. For the noisy experiment we apply the densitymatrix method with $k=1024$ shots and compute the HOP value according to the definition above.

4.2 Comparison of layer free optimization and optimization with layers

We display the results for the two objectives and three metrics in parity plots. In these plots, we scatter the solution values of the computed instances, where the $x$-value corresponds to the metric value of the non-layered instance, and the $y$-value represents the value of the layered variant. The dashed red line marks the line of parity, indicating where both instance solutions agree on the considered metric. We only consider the instances where both the layered and non-layered approach converged after a given time limit of $500\text{\,}\mathrm{s}$; all others are omitted. The comparison of results for the depth objective is presented in Figure 4, while the results for the number of SWAPs are shown in Figure 5. In both figures, the columns correspond to the hardware graphs (Linear, Grid, and Y), and the rows correspond to the metrics (depth, number of SWAPs, and unweighted depth). Additionally, each plot title identifies the combination of hardware graph, objective, and metric used.

In Subfigures 4(a) - 4(c) and 5(d) - 5(f) it can be seen that for all hardware graphs, the non-layered approach outperforms the layered one when comparing the metric used for optimization. The effect is most present for the Y graph instances, with over three more SWAPs on average and a depth longer than $37$ units of time. On the other hand, the non-layered approach provides the least advantage for the grid-graph instances with $0.36$ more SWAPs on average and an increase of $0.24$ in circuit duration. This finding is expected, given that the Grid graph has the strongest connectivity. Additionally the Y-graph has a central node; for a Y graph with $4$ nodes for example, a SWAP is expected in each layer with more than one gate in the layered approach. In between lie the instances with a Linear hardware graph, with a noticeable increase in SWAPs of $0.46$ and an average duration $2.22$ units longer than with the non-layered approach. Additionally 4(d)-4(f) show that optimization for the depth also has a positive effect on the number of SWAPs, where the non-layered approach is favorable as well. This is mainly due to the long duration of the SWAP gate, which significantly increases the execution time of the circuit when present. On the other hand, optimization for the number of SWAPs does not seem to have a significant effect on the circuit depth as seen in 5(a) - 5(c), especially on Linear and Grid hardware graphs. Lastly there is little to no effect on the unweighted depth for both optimization targets as seen in 4(g) - 4(i) and 5(g) - 5(i). This highlights the importance of taking gate durations into account, when optimizing for the actual makespan of the circuit.

Additionally we take a closer look at the results of the metric comparison with the same optimization target in 4(a) - 4(c) and 5(d) - 5(f). As many solution values agree for the same instance in the parity plots, we additionally compute another metric, the relative mean deviation RMD; Table 3 shows these results. The number of instances of each graph and objective combination, which are successfully solved before timeout is denoted by $N^{S}$. The number of instances where both the layered and non-layered approach returned the same objective value is denoted by $N^{=}$. The relative mean deviation is computed as the mean of the deviations of all solution values from the layered and non-layered instances:

[TABLE]

where $y_{i}^{L}$ and $y_{i}^{NL}$ are the objective values from the layered and non-layered instances, respectively.

Since many instances for the Linear and Grid hardware graphs agree with respect to the metric used, we also compute the relative mean deviation for instances that did not yield the same value, denoted as $\operatorname{RMD}^{\neq}$. This metric is of interest as for the fact, that the instances have been solved to optimality by Algorithm 1. Therefore, instances where both approached agree on their objective value have no potential of optimization at all, when considering a non-layering vs. a layering approach.

Lastly we display the mean of the HOP values of the instances computed and their difference in Table 4. The HOP value means range between $64\%$ and $71\%$, with differences in the sub-percentage area. This is because we do not explicitly optimize for the HOP value; however, a positive effect is observed for the non-layered approach. The most noticeable difference of layered vs. non-layered approach can be seen in the Y-graph instances, as for the objective values in 4(c) and 5(f). The difference for the other hardware graphs on the other hand is small. This can be explained by the high agreement of solutions for Grid and Linear graphs, in contrast to the instances on Y-graphs. Altogether, except for the number of SWAPs objective for the Grid hardware graph, the non-layered approach dominates the layered one with regard to the HOP mean.

5 Conclusions and future work

In this paper, we analyzed the effect of considering or ignoring layers when optimizing the qubit mapping problem with respect to the minimization of circuit depths or number of SWAPs while also considering the gate execution time. We developed a custom and flexible branch and bound algorithm to solve this problem, accompanied by a novel bounding function. We then showed that when the hardware graph is sparsely connected (such as the linear graph or the Y graph), the difference between considering and ignoring layers can be significant.

The flexibility of the algorithm offers the opportunity to easily test and experiments with new ideas. Here are some examples:

• •

Bounding heuristics: the bounding function proposed in this paper is so-called admissible, meaning that the algorithm is guaranteed to find the optimal solution (given enough time). Non admissible bounding functions would allow the algorithm to possibly cut more branches, speeding up the solution process but loosing the optimality guarantees.

• •

Selection heuristics: while choosing the node with the lowest bound has been shown to produce smaller trees when looking to prove optimality [8], different selection functions can produce a more heuristic behavior. For example, by limiting the number of nodes at a certain depth of the search tree, one could implement a beam-search heuristic.

• •

Noisy qubits: the algorithm currently ignores the fact that some physical qubits can be more noisy than others and should be avoided as much as possible. Interestingly, this noise can also change over time, and that could also be taken into account.

• •

Objective functions: the number of SWAPs and the depth of the circuit are two common proxy functions to evaluate the quality of a compiled circuit. However, other objectives functions such as the minimization of the error rate (suggested in [14]) could be interesting to explore.

Acknowledgment

We would like to thank the Research Council of Norway for providing partial funding for this work through project number 332023.