Hybrid Cryptographic Monitoring System for Side-Channel Attack Detection on PYNQ SoCs

TL;DR

This paper introduces a lightweight, real-time hybrid detection system combining statistical and machine learning methods to identify side-channel attacks on AES-128 encryption in embedded PYNQ SoCs, enhancing security without hardware modifications.

Contribution

It presents a novel dual-detection framework that integrates statistical thresholds and ML classifiers for effective side-channel attack detection on resource-constrained embedded systems.

Findings

ML approach outperforms static thresholds in accuracy

Framework operates in real-time on embedded platforms

No modification of AES internals required

Abstract

AES-128 encryption is theoretically secure but vulnerable in practical deployments due to timing and fault injection attacks on embedded systems. This work presents a lightweight dual-detection framework combining statistical thresholding and machine learning (ML) for real-time anomaly detection. By simulating anomalies via delays and ciphertext corruption, we collect timing and data features to evaluate two strategies: (1) a statistical threshold method based on execution time and (2) a Random Forest classifier trained on block-level anomalies. Implemented on CPU and FPGA (PYNQ-Z1), our results show that the ML approach outperforms static thresholds in accuracy, while maintaining real-time feasibility on embedded platforms. The framework operates without modifying AES internals or relying on hardware performance counters. This makes it especially suitable for low-power, resource-constrained systems where detection accuracy and computational efficiency must be balanced.

Equations

$$T=\mu +3\times \frac{\max -\min }{n}$$

Full text

AES, anomaly detection, timing attack, side-channel security, FPGA, PYNQ, lightweight cryptography

††copyright: none††copyright: acmlicensed††journalyear: 2025††conference: International Conference for High Performance Computing, Networking, Storage, and Analysis (SC25); November 16–21, 2025; St. Louis, MO

1. Introduction

The Advanced Encryption Standard (AES) has become the cornerstone for securing data across diverse platforms, from cloud data centers to embedded IoT devices (karakchi2025toward, ). Among its variants, AES-128 remains widely adopted for its optimal balance between performance and security. However, despite its cryptographic soundness, real-world implementations often leak unintended information on the side channel (kocher1996timing, ; bernstein2005cache, ), opening the door to physical attacks or timing-based attacks.

Timing attacks exploit variations in encryption latency to infer secret keys. Kocher’s seminal work (kocher1996timing, ) exposed how control flow and cache behavior can leak timing differences. Bernstein extended this by showing that even remote attacks could succeed on shared systems (bernstein2005cache, ), highlighting how software-only observations can defeat theoretically secure algorithms. Fault injection attacks, such as differential fault analysis (DFA) (biham1997differential, ), manipulate the computation process, potentially revealing internal state values or leading to predictable ciphertext corruption.

Countermeasures such as constant-time coding and masking (cryptoeprint:2017:106, ; choi2020advanced, ) mitigate some risks but often require hardware modifications or introduce runtime overhead, which is infeasible in low-power or embedded systems. Some defenses rely on hardware duplication or error-detection codes, but these are impractical for widespread deployment in low-cost systems.

Recently, machine learning-based anomaly detection has gained traction, analyzing traces like power or execution time to detect malicious behavior (wang2021machine, ; yu2023ml, ; zhang2020random, ; abdellatif2021ml, ; liu2023deep, ). Although promising, such approaches typically require large labeled datasets and computationally heavy models, making real-time deployment on embedded devices difficult.

In this work, we develop a lightweight threshold-based timing anomaly detector Figure 1 that flags encryption anomalies using only execution time. This method is non-intrusive, requires no access to internal AES logic, and avoids external sensors, making it ideal for embedded deployments. To further enhance granularity, we complement this with a supervised machine learning approach that uses timing and ciphertext features.

We evaluated both methods on a multicore CPU and the Xilinx PYNQ-Z1 FPGA SoC (xilinxpynqz1, ), comparing performance, accuracy, and feasibility. Our results provide insight into how statistical and ML-based detectors behave under controlled anomaly injection and serve as a foundation for future hybrid cryptographic monitoring systems.

2. Methodology

In this work, we develop and evaluate a statistical timing-based anomaly detection framework to enhance the security of AES-128 encryption. Our methodology consists of anomaly injection, parallel encryption execution, timing measurement, and threshold-based anomaly detection. We evaluated this methodology on both a standard multi-core CPU (8 logical cores and 3.2 GHz) environment and a Xilinx PYNQ Z1 platform, which is equipped with a dual-core ARM Cortex-A9 processor.

2.1. Anomaly Injection Mechanism

To simulate potential threats, we inject two types of anomalies into selected encryption blocks:

• •

Timing Delay Injection: A short delay (5–20 ms) is added before encryption to simulate cache contention or intentional software slowdowns, mimicking timing-based side-channel behavior.

• •

Fault Injection (Bit Flip): The first byte of the plaintext block is XORed with 0xFF before encryption, simulating data corruption from voltage glitches or electromagnetic interference.

Each anomaly-injected block is labeled malicious. The injection ratio $r$ determines the percentage of blocks modified (typically 10%–30%). These modifications ensure that both latency- and content-based deviations are present in the data set. The complete procedure is described in Algorithm 1.

AES-128 encryption is implemented in Electronic Code Book (ECB) mode using the PyCryptodome library (pycryptodome, ). Each plaintext input is a 16-byte randomly generated block. We deploy the encryption framework on the PYNQ Z1 platform, which enables parallel processing using Python’s multiprocessing module. This setup mimics real-time cryptographic execution under multi-core embedded environments.

2.2. Timing-Based Anomaly Detection

The threshold-based detection uses the following statistical rule:

[TABLE]

where $\mu$ is the mean encryption time, $\max$ and $\min$ are the observed maximum and minimum times, and $n$ is the total number of blocks. This rule is inspired by the empirical ”3-sigma” rule used in statistical outlier detection (hand2001idiot, ). Any block whose execution time exceeds $T$ is flagged as potentially malicious.

2.3. Machine Learning-Based Detection

To overcome the limitations of timing-only detection, we implement a supervised machine learning method using a Random Forest classifier. Features extracted from each block include encryption time and ciphertext bytes. The classifier is trained to detect anomalies such as fault-injected or delay-affected blocks. Algorithm 2 describes the ML-based anomaly detection procedure.

2.4. Experimental Setup

The experiments were carried out on two platforms:

• •

CPU Platform: A multi-core desktop with Intel i7 CPU and 16GB RAM, using Python’s multiprocessing for parallel encryption and timing.

• •

Embedded Platform: Xilinx PYNQ-Z1 featuring a dual-core ARM Cortex-A9 CPU running lightweight Linux. All logic was implemented in native Python using onboard resources.

In both setups, timing logs, anomaly labels, and output metrics were stored for offline analysis. This ensured a consistent dataset for both threshold and ML-based evaluation.

3. Deployment and Evaluation

We evaluated both detection methods on a multi-core CPU and the PYNQ-Z1 FPGA, representing general-purpose and embedded environments.

The threshold method offered fast, low-overhead detection but missed subtle anomalies. The Random Forest classifier, using timing and ciphertext features, improved accuracy with inference latency under 5 ms on the PYNQ-Z1.

Both approaches performed consistently across platforms. The ML model used under 30% of FPGA resources, confirming its suitability for embedded use. Thresholding ensures speed and simplicity, while ML enhances detection in complex scenarios. Future work includes integrating side-channel features and tighter hardware coupling.

Acknowledgements.

This work was supported by the Office of Undergraduate Research and the McNair Junior Fellowship at the University of South Carolina. The authors thank Rye Stahle-Smith for his assistance with hardware testing and experimental setup.