SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics

TL;DR

This paper introduces SCE-NTT, a superconducting hardware accelerator for the Number-Theoretic Transform, achieving over 100x speedup compared to CMOS, enabling scalable and energy-efficient homomorphic encryption computations.

Contribution

The paper presents the first superconducting NTT accelerator using SFQ logic, with a novel pipelined architecture and a new cell library, significantly outperforming existing CMOS solutions.

Findings

Achieves 531 million NTT/sec at 34 GHz

Over 100x faster than CMOS equivalents

Scales to larger NTT sizes with sub-microsecond latency

Abstract

This research explores the use of superconductor electronics (SCE) for accelerating fully homomorphic encryption (FHE), focusing on the Number-Theoretic Transform (NTT), a key computational bottleneck in FHE schemes. We present SCE-NTT, a dedicated hardware accelerator based on superconductive single flux quantum (SFQ) logic and memory, targeting high performance and energy efficiency beyond the limits of conventional CMOS. To address SFQ constraints such as limited dense RAM and restricted fanin/fanout, we propose a deeply pipelined NTT-128 architecture using shift register memory (SRM). Designed for N=128 32-bit coefficients, NTT-128 comprises log2(N)=7 processing elements (PEs), each featuring a butterfly unit (BU), dual coefficient memories operating in ping-pong mode via FIFO-based SRM queues, and twiddle factor buffers. The BU integrates a Shoup modular multiplier optimized for a small area, leveraging precomputed twiddle factors. A new RSFQ cell library with over 50 parameterized cells, including compound logic units, was developed for implementation. Functional and timing correctness were validated using JoSIM analog simulations and Verilog models. A multiphase clocking scheme was employed to enhance robustness and reduce path-balancing overhead, improving circuit reliability. Fabricated results show the NTT-128 unit achieves 531 million NTT/sec at 34 GHz, over 100x faster than state-of-the-art CMOS equivalents. We also project that the architecture can scale to larger sizes, such as a 2^14-point NTT in approximately 482 ns. Key-switch throughput is estimated at 1.63 million operations/sec, significantly exceeding existing hardware. These results demonstrate the strong potential of SCE-based accelerators for scalable, energy-efficient secure computation in the post-quantum era, with further gains anticipated through advances in fabrication.

Tables

Table 1. TABLE I: Operation Decomposition of CKKS Scheme For Different coprocessors

Operations	Host	CMOS coprocessor	SCE-NTT coprocessor
Mod Up/Down	Data Transfer	Decode, Modular Mult, Modular Add/Sub	NTT, INTT
Relinearization	Data Transfer	Decode, Modular Mult, Modular Add/Sub	NTT, INTT
Rescale	Data Transfer	Decode, Modular Mult, Modular Add/Sub	None
Homomorphic Add/Sub	Data Transfer	Decode, Modular Add/Sub	None
Homomorphic Mult	Data Transfer	Decode, Modular Mult, Modular Add/Sub	NTT, INTT

Table 2. TABLE II: Comparison between Barrett and Shoup Mod multiplier

Design	Logic cell Count	Splitter Count	DFF Count	JJ Count
Barrett Mod Multiplier	31,848	108,738	48,060	1,342,704
Shoup Mod Multiplier	18,583	56,324	18,433	664,873

Table 3. TABLE III: Post synthesis result for whole NTT design. The clock cycle for the design is 29.4 ps, and the throughput is 34 GHz, which translates to 531M (mega) NTT/sec.

Component	Logic Cell Count	Total JJ	Latency
BU for each PE	19,838	969,774	79 cycles
Total Datapath	138,866	6,788,446	79 cycles
Memory block for the last PE (max)	-	182,474	69 cycles
Total memory	-	1,099,309	69 cycles
Total design	-	7,887,755	1,036 cycles

Table 4. TABLE IV: Junction parameters.

Parameter	Default Value	Description
Ic	GLOBAL_$I_{C0}$	Junction critical current [A].
BetaC	GLOBAL_${\beta }_C$	Junction Stewart-McCumber parameter.
JJarea	Ic/FABPROC_Jc	Junction area [$m^2$].
R0	$\sqrt{\frac{{\beta }_C\ast {\Phi }_0}{2\ast \pi \ast I_C\ast C_s\ast A}}$	Junction shunt resistor [$\Omega$].
Ljp	GLOBAL_LJP	Junction parasitic inductor [H].

Equations

$$A(x)=\sum _{i=0}^{N-1}{a}_i{x}^i\text{ mod }q$$

$$A_r=A({\omega }_N^r)$$

$$A_{r+\frac{N}{2}}=A({\omega }_N^{r+N/2})$$

$$a_i$$

$$a_{i+\frac{N}{2}}$$

$$({\mathbf{i}}_6{i}_5{i}_4{i}_3{i}_2{i}_1{\mathbf{i}}_0{)}_b$$

$$({\mathbf{i}}_5{i}_4{i}_3{i}_2{i}_1{i}_0{\mathbf{i}}_6{)}_b$$

$$({\mathbf{i}}_4{i}_3{i}_2{i}_1{i}_0{i}_6{\mathbf{i}}_5{)}_b$$

$$A_{OUT}=(A_{IN}+B_{IN}\ast TW)\mathrm{mod}q$$

$$B_{OUT}=(A_{IN}-B_{IN}\ast TW)\mathrm{mod}q$$

$$N\ge \frac{\lambda +110}{7.2}\log (P\cdot q_L)$$

Full text

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I Introduction

Superconductor electronics (SCE) is a promising technology for computation and accelerators in the post-CMOS era [1]. Despite the current lack of advanced fabrication processes for SCEs, the high frequency and non-dissipative nature of these circuits provides a two to three orders of magnitude energy efficiency gain at the same performance (iso-performance level) as CMOS.

Several superconductor logic families, such as Rapid single flux quantum (RSFQ), energy-efficient RSFQ (ERSFQ) [2], and adiabatic quantum-flux parametron (AQFP) [3], are introduced in the literature. However, the lack of dense memory, limited fanin/fanout, and deep pipeline nature of these logics requires support from advanced circuit methodologies. Much work on SCE library cell design and characterization, circuit simulation and margin, power and timing analysis, logic synthesis, and physical design, as well as biasing networks and dual clocking architectures, was performed as part of the IARPA C3 and SuperTools programs [4, 5]. To show the feasibility of this technology, fully functional SCE-based microprocessor prototype chips have been demonstrated in RSFQ [6] and AQFP logic [7].

The deeply pipelined nature of SCE logic makes it more suitable for applications with streaming data processes such as fast Fourier transform (FFT) or number theory transform (NTT). Therefore, the most process-intensive part of FHE, NTT, can benefit from SCE logic. Fully homomorphic encryption (FHE) is a cryptosystem that allows operations to be evaluated on encrypted data without decryption [8]. It has been one of the most promising solutions that makes it possible to outsource computation and securely aggregate sensitive information from individuals, corporations, and government agencies.

With the potential development of large-scale quantum computers, existing public-key cryptography protocols (such as RSA and ECC) become insecure due to the quantum Fourier transform and Shor’s algorithm [9]. As a prime candidate for quantum-resistant encryption algorithms, FHE enables users and developers to perform computations directly on the ciphertexts, obtaining results identical to exact computations on plaintexts. After Gentry’s first construction of fully homomorphic encryption [8], several research studies [10, 11, 12, 13, 14, 15] have improved the efficiency of FHE schemes.

FHE schemes can be classified into different types based on the data types they support. The most common FHE schemes are the following.

The Fast Homomorphic Encryption from Learning with Errors (FHEW) scheme [16, 17] works primarily on Boolean logic. 2. 2.

The Brakerski-Gentry-Vaikuntanathan (BGV) and Brakerski-Fan-Vercauteren (BFV) schemes [18, 19] support modular arithmetic over finite fields. 3. 3.

The Cheon-Kim-Kim-Song (CKKS) scheme [20] relies on approximate computation.

All these schemes are developed based on the mathematical hardness of ring learning with error, where noise is added during encryption and computations on the ciphertext. Therefore, FHE schemes require the ciphertext modulus $q$ to be large enough to accommodate noise growth without corrupting useful information.

There are two main categories of memory access algorithms that are used to execute the NTT operation efficiently: in-place and out-of-place memory access algorithms. The in-place memory access algorithm writes all intermediate results at the location from which they are read. Consequently, this approach necessitates a data rerouting network and random access memory to correctly read the two coefficients as a pair, accounting for accessing different coefficients across NTT stages. On the other hand, out-of-place memory access emerges as a good candidate, allowing intermediate results to be stored in different locations compared to their read locations [21].

As a result, simplifying the data rerouting network and random access memory becomes feasible, offering potential benefits to SFQ circuits. Additionally, multiple memories are used to mitigate write-after-read (WAR) hazards resulting from distinct read and write locations. Regarding hardware implementation, we need butterfly units (BUs) to perform butterfly operations in different stages, the twiddle factor memory to store the required twiddle factors, and the coefficient memory to store all intermediate results.

This paper presents an FHE accelerator that uses superconductor SFQ logic and memory. Meanwhile, the shift-register-based memory replaces the random access memory, and the corresponding control logic is significantly simplified. More specifically, we will focus on designing and demonstrating an accelerator for performing the number-theoretic transform (NTT) operation, which is the critical computational task in nearly all FHE operations, including ring multiplication, key switch, mod switch, and bootstrap.

II Homomorphic Operation

Most ongoing research efforts focus on developing optimizations for the CKKS scheme [22, 23, 24]. The operations in the FHE schemes are performed in the ring introduced in [25, 26]. The ring can be denoted as $R_{q}=\mathbb{Z}_{q}[x]/\phi(x)$, where $Z_{q}[x]$ contains polynomials with coefficients in the range of $[0,q)$ and $\phi(x)$ is a reduction polynomial, typically equal to $x^{N}+1$.

The polynomial degree of $\phi(x)$ limits the degree of polynomials in $R_{q}$. For example, when $\phi(x)$ equals $x^{4}+1$, the maximum polynomial degree for a polynomial inside $R_{q}$ is $3$. In addition, ciphertexts are stored in the polynomial, where the degree of a polynomial is usually denoted as N and ranges from 1,024 to 65,536. The primitive computations over ciphertext are mainly composed of polynomial multiplication over a ring $R_{q}=\mathbb{Z}_{q}[x]/(x^{N}+1)$, where $q$ is the modulus of the coefficients of the polynomials and the maximum degree of polynomials in this ring is equal to $N-1$. Consequently, ciphertext addition and multiplication operations correspond to polynomial additions and multiplications.

Instead of directly computing polynomial multiplication by matrix multiplication, which results in a time complexity of $O(N^{2})$, the NTT reduces the time complexity to $O(N\log(N))$. This reduction is achieved by evaluating the polynomial:

[TABLE]

at different powers of $N$-th primitive root $\omega_{N}$ (that is, twiddle factor). The $N$-th primitive root is a value that satisfies $\omega_{N}^{i}\not=1\text{ mod }q$ for $i\in(0,N)$ and $\omega_{N}^{N}=1\text{ mod }q$. Based on the divide-and-conquer method, this original problem can be separated into two sub-problems, as expressed as:

[TABLE]

where $\omega_{N}^{r+N/2}=-\omega_{N}^{r}$ based on the halving lemma of the twiddle factor. Additionally, the sub-problems can be further separated. Next, during the merge step, we can apply radix-$2$ Cooley-Tukey (CT) butterfly operations to compute the values of $A_{r}$ and $A_{r+N/2}$, which consist of modular multiplication, modular addition, and modular subtraction. Therefore, the NTT operation requires $s=\log_{2}(N)$ stages, each containing $N/2$ number of CT butterfly operations.

Following the divide-and-conquer method, in the first NTT stage, the CT butterfly operation can be expressed as:

[TABLE]

where $i\in[0,N/2)$. Two coefficients are processed as a pair of coefficients: $(a_{i},a_{i+N/2})$. Notice that the difference between coefficient indices inside a pair will decrease from $N/2$ in the first NTT stage to $1$ in the last NTT stage. In other words, when the index of a coefficient is in the binary representation $(i_{s-1}i_{s-2}\cdots i_{1}i_{0})$, the bit that is different between coefficient indices inside a pair will vary from $i_{s-1}$ in the first NTT stage to $i_{0}$ in the last NTT stage.

III FHE Accelerator

To develop an FHE accelerator using superconductive SFQ logic and memory, we propose the architecture depicted in Fig. 1. The design comprises two coprocessors: a CMOS-FHE coprocessor operating at room temperature and an SCE-NTT coprocessor operating at cryogenic temperatures. The CMOS-FHE coprocessor facilitates data transfer between the host and the SCE-NTT coprocessor since dense on-chip SFQ memory with random access has not yet been realized. The CMOS-FHE coprocessor can also perform modular additions and multiplications to accelerate various auxiliary operations in an FHE system. The SCE-NTT coprocessor is employed to speed up the NTT and inverse NTT (iNTT) operations utilizing the ultra-high-frequency switching nature of the SFQ logic.

In the CKKS scheme, operations can be broken down into modular addition/subtraction, modular multiplication, NTT, and INTT operations. Table I delineates the specific operations handled by each coprocessor. Specifically, in this seedling project, our focus is on designing and demonstrating an accelerator (NTT unit) for performing the NTT and INTT operations, which are critical computational tasks in various FHE operations, including Homomorphic Multiplication, Mod Up/Down, and Relinearization.

IV Efficient NTT Implementation

Figure 2 provides an overview of our NTT design with 128 points (NTT-128) using SFQ circuits. The design comprises seven processing elements (PEs), with each PE handling butterfly operations for one NTT stage. The data flow in the proposed NTT-128 design follows a pipeline structure, progressing from the first PE to the last PE. Each PE comprises two coefficient memories, each with N slots operating in a ping-pong manner to store all intermediate results to avoid WAR hazards since the read and write addresses of the coefficients are different. Additionally, a BU is included to compute butterfly operations within an NTT stage. Furthermore, two twiddle-factor queues are incorporated to store precomputed values.

IV-A NTT Architecture

The proposed NTT operates in a fully pipelined manner, while the two coefficient memories operate in a ping-pong manner. During computation, one coefficient memory is used to store intermediate results from the primary input or previous PE, and the other coefficient memory provides data from previous NTT operations to the BU for butterfly operations. Meanwhile, the twiddle factor (TW) queues provide the corresponding TWs to the BUs, and the pipelined BU executes butterfly operations for an NTT stage, generating the results as the primary output of a PE.

Our design utilizes the first-in-first-out queues (FIFO), which are implementable using shift registers, to instantiate coefficient and twiddle factor memories. This approach, with the proposed memory access pattern, eliminates the need for complex random access memory (RAM) in the SFQ circuit. Figure 3 illustrates the read and write sequences of the coefficient memory. This pattern will be applied consistently across all coefficient memories in various PEs.

Based on the property of the FIFO, the write operation can only be performed at the tail of the queues, whereas the read operation can only be performed at the head of the queues. Each coefficient memory consists of four queues that can store or generate two coefficients in one clock cycle. The numbers in Figure 3 denote the sequence for read and write operations. For example, we will write two coefficients to queues 0 and 1 in the first clock cycle. Next, the corresponding coefficients will be shifted to the heads of the queues.

To establish the connection between coefficient indices and memory locations, we use the binary representation of the coefficient index i to denote the memory location of the coefficient $a_{i}$. Assume that two coefficients are provided to the first PE in the natural order (e.g., $a_{0}$ and $a_{1}$ in the first cycle, followed by $a_{2}$ and $a_{3}$). Following the write access pattern shown in Figure 3, the first half of the coefficients will be stored in queues 0 and 1, and the last half will be stored in queues 2 and 3. We can, therefore, derive that the coefficient $a_{i}$ is stored at the memory location:

[TABLE]

where the most significant bit $(i_{0})$ and the least significant bit $(i_{6})$ are in bold since they serve as bank enables for four queues. The rest of the bits ($i_{5}$ to $i_{1}$) are the corresponding addresses of a coefficient inside a queue. As these storing operations are performed, $a_{0}$ and $a_{1}$ in queues 0 and 1 are shifted to the heads of the queues. Therefore, the coefficient $a_{i}$ is stored in the location specified in equation (4).

After all coefficients are stored inside these four queues, we start the read operations following the sequence shown in Figure 3. During read operations, two coefficients stored in queues 0 and 2 or 1 and 3 are obtained in one clock cycle. Therefore, the indices of coefficients within a coefficient pair differ in $i_{6}$, meeting the requirement for inputs to butterfly operations in the first NTT stage. The corresponding bits $(i_{5}i_{4}i_{3}i_{2}i_{1}i_{0})_{b}$ of the coefficient indices within a pair of coefficients will automatically be incremented according to the property of the FIFO. While coefficient memory ’0’ generates coefficients for inputs of the BU, coefficient memory ’1’ stores coefficients for the next NTT operation.

The results of butterfly operations in the first PE will be applied to the second PE. The input sequence of the coefficient for the second PE is identical to the read sequence in the first PE since the BU is a pipelined design. Consequently, after applying the same write sequence as shown in Figure 3 for coefficient memory in the second PE, the coefficient $a_{i}$ is stored at the memory location:

[TABLE]

where coefficient pairs are stored in queues 0 and 1, followed by queues 2 and 3. Therefore, $i_{6}$, which is the different bit inside coefficient indices inside a pair in the first stage, is moved to the least significant bit of the addresses. Similarly, following the same read sequence, two coefficients with different values on $i_{5}$ will be obtained with the read address $(i_{4}i_{3}i_{2}i_{1}i_{0}i_{6})_{b}$. Based on the retrieved coefficient pairs, we can perform butterfly operations in the second NTT stage. In addition, we can derive the memory layout in the third PE as,

[TABLE]

This process can be repeated until the last PE. The efficient computation of a 128-point NTT operation is achieved through the proposed memory access pattern utilizing seven PEs, with each PE performing butterfly operations for a specific NTT stage.

Since the read-access pattern for the coefficients is fixed across different PEs, the sequence of TWs will also be fixed and easily implemented using a wrap-around FIFO, where the input and output are connected. Additionally, based on the property of the divide-and-conquer method, the number of required TWs will vary between different PEs, with the last PE requiring the largest number of TWs (that is, 64). Furthermore, another TW queue is denoted as TW’ (also called TWP) in Figure 2. The TW’ queue stores precomputed values corresponding to twiddle factors within the TW queue, resulting in the same number of memory slots as the TW queue. These precomputed values are used to save hardware area for the modular multiplication unit.

IV-B Butterfly Unit Design

The BU comprises a modular multiplier, a modular subtractor, and a modular adder. For modular multiplication $(C=A\times B\text{ mod }q)$, we have three prevailing types of design: Shoup modular multiplier, Montgomery modular multiplier, and Barrett modular multiplier. The details of each design can be found in [27, 28, 29]. As the values of B in the butterfly operations are precomputed twiddle factors, we can take advantage of the Shoup modular multiplier. This approach requires a smaller hardware area, aided by the value of B’, which is associated with both B and q. These B’ values are stored in the TW’ queue.

Since the RSFQ circuit is deep-pipelined, meaning that every logic cell requires a clock signal, we need to insert path-balancing DFFs to balance the data path for each cell. Based on our result from [5], as the circuit size grows, the number of path-balancing DFFs can take more than 60$\%$ of the whole design. Furthermore, since each cell requires a clock signal and the RSFQ circuit requires a specific cell called a splitter to propagate the corresponding signal to multiple fanouts, we need a large clock tree to distribute this signal. The large amount of path-balancing DFFs makes the situation even more complicated [30]. Therefore, our preferred design is an architecture that performs an operation in parallel and has a smaller circuit depth.

The Montgomery modular multiplier requires Montgomery conversion before it can perform a modular operation, resulting in a specialized converter in the BU. Hence, we select between the Barrett modular multiplier and Shoup modular multiplier, whose schematics are shown in Fig. 4 and Fig. 5.

Based on the schematic, the Barrett modular multiplier comprises a multiplier, two half multipliers, path-balancing DFFs with a depth of two half multipliers, and a modular subtractor. The Shoup modular multiplier comprises three half multipliers, path-balancing DFFs with a depth of one-half multiplier, and one modular subtractor. The circuit depth is two half multipliers and one modular subtractor. The synthesis result for the Barrett and Shoup modular multiplier is shown in Table II.

As shown in Table II, the JJ count for the Shoup is around half of the Barrett modular multiplier due to the small number of path-balancing DFFs and Splitters. Therefore, we use the Shoup modular multiplier in our design.

The Kogge-Stone adder fits our design best because it only requires log(N) levels to finish the design, which saves a large area for our design. In comparison, the subtractor is just one more layer to convert the number to its two’s complement.

As shown in Fig. 6, the yellow block is the Shoup modular multiplier, the green block is the modular adder, and the orange block is the modular subtractor. The synthesis results for BU and the memory block are shown in the Table. III.

V RSFQ Circuit Implementation

Such a large circuit synthesis needs a complete cell library with compound functions such as multiplexors and a one-bit full adder. A new cell library with the MIT LL SFQ5ee process [31] in mind was designed using a hierarchical and parameterized approach. All component values are designated as parameters. These values are scaled according to the parameters of the fabrication process. This approach allows frequently utilized circuit structures, or ”components,” to be defined as distinct subcircuits, promotes reusability and scalability, facilitates library retargeting to other fabrication processes, accelerates the cell design process, and optimization to subcomponents automatically propagates through the entire library.

Cell Library Structure

The RSFQ cells are constructed using smaller parameterized components known as subcircuits. Each subcircuit comprises basic circuit elements such as inductances and resistances. The switching element in the RSFQ circuits is JJ. The schematic of a JJ with parasitic parameters is shown in Fig. 7. The parameters that are controlled for cell design are demonstrated in Table IV. The program gets the parameters and, based on that, forms the cell library that comprises global parameters coming from the fabrication process, components that house all the smaller subcircuit components routinely used in cells, base cells that store all the logic, interface, and buffer cells, standard cells that contain cells with standard connections, PTL cells containing cells with Passive Transmission Line (PTL) interfaces designed to connect to PTLs and includes integrated PTL transmitter and receiver circuits.

An OR base cell structure is shown in Fig. 8. Standard cells are designed for direct connection to each other. The input and output pins incorporate integrated standard transmitter and receiver cells called the HJTL (half Josephson transmission line). All standard cells use identical transmitters and receivers, ensuring stable interconnects, as demonstrated in Fig. 9. Our cell library contains over 50 standard cells, with all base logic cells operating at 50 GHz.

PTL interconnects

Passive transmission lines are implemented as striplines with ground planes above and below each conductor. To decrease the layout footprint of the interconnects, the characteristic impedance has been increased from the previous $5.4\text{\,}\mathrm{\SIUnitSymbolOhm}$ presented in [5] to $11\text{\,}\mathrm{\SIUnitSymbolOhm}$ in the new library to increase the routing density. This results in the width of the signal line changing from a width of $4.6\text{\,}\mathrm{\SIUnitSymbolMicro m}$ to $2\text{\,}\mathrm{\SIUnitSymbolMicro m}$, effectively doubling the routing capacity for a given area.

VI SRM and Controller Design

As stated, memory implementation in SFQ technology is a challenge. Therefore, the architecture design aimed at using SRM is more feasible for SFQ design and meets the timing closure confirmed by behavioral and circuit simulations up to 34 GHz. Fig. 2 shows a high-level diagram of a single PE stage, which includes the BU, memory subblocks, a controller, and some glue logic. Notice that there is an SRM for storing coefficients, circular shift register memories (CSRM) for storing TW and TW’s data, a memory access controller (MAC) to orchestrate the data movement, and glue logic to tie all the main memory components together, including asynchronous merger-based MUXes and delay elements.

The memory subblock is clocked at 34 GHz (29.4 ps clock period) and has a control signal to commence loading of TW data (TW_LD) and notify that the last TW data has been loaded (TW_RDY). There are five 32-bit input ports, two for coefficient input data (DI0, DI1), two for the Valid bit for data (VI0, VI1), and loading initialization of 32-bit data for TW CSRM (TWI). The input port for loading the initialization of 32-bit data for TW’s CSRM needs 33 bits.

The connections between the PEs are shown in Fig. 10 and the primary I/O control and loading signals. The difference between each memory subblock design is the TW memory size, starting with a 1-stage CSRM for PE0 to a 64-stage CSRM for PE6 ($\text{CSRM stage size}=2^{i}$ for $\text{PE}_{i}$). The latency of this memory (clk-to-q) is 7.5 cycles (219 ps), the output spread is $\pm$2.5 ps, and setup and hold times are zero and 5 ps, respectively. The coefficient memory has two banks, and the bank size is 4$\times$32$\times$32 bits. TW memory has two banks, and each bank’s maximum length is 64 $\times$ 33 bits.

VI-A Full-Custom Design Infrastructure for Memory

The memory subblock of each PE is designed using a full custom design flow illustrated in Fig. 11. We use Synopsys Custom Compiler for gate-level, full-custom design of the memory system, which includes the hierarchical management of the memory subblock and components. The design is primarily done at the gate level using a schematic entry tool with access to the cell library database. Netlists are generated from schematics and processed for analog and digital simulations. The functionality of the design was verified by comparing the analog simulation results from the JoSIM simulator to the high-level Python model.

VI-B Full-Custom Design of SRM and MAC

The design of the memory subblock of the NTT processing element comprises four main subcomponents: coefficient SRM, twiddle factor CSRM, MAC, and Glue Logic.

VI-B1 Coefficient SRM

As seen in Fig. 2, two banks of coefficient SRMs are denoted as CM0 and CM1. When one bank is in the ”read” mode, the other is in the ”write” mode. When a bank is filled with data, it will switch to the ”read” mode to start reading the data into the BU of the PE. Each bank comprises 4 SRM-based queues. Each queue is a 32-stage 32-bit SRM. A simplified diagram of the memory bank is shown in Fig. 12. Note that the term ”queue” means that a queue is implemented as a standard shift register where data is loaded from the tail end, and on each shift cycle, data is shifted towards the head end of the shift register. Another important distinction is that the SRMs are ”triggered” by the MAC at appropriate times rather than a system clock that always clocks the SRM on every cycle. So, what traditionally appears as a ”clock” input for the SRM will, from now on, be referred to as the trigger (TRIG) input of the SRM.

The inputs to the coefficient SRM banks are broadcast to all possible destinations, whether they are the correct destination for that particular cycle or not. That is, DIO data is broadcast to QUEUE0 and QUEUE2, whereas DI1 data is broadcast to QUEUE1 and QUEUE3. To DEMUX the broadcasted inputs appropriately, we designed a self-resettable write port comprising a resettable DFF (DFFR). This mechanism is illustrated in Fig. 13 with the DFFR highlighted in green. The coefficient SRM consists of dual-flow clock-based shift registers with a write port based on a self-resettable DFFR. For each PE, there are two banks of coefficient memories. Each bank comprises four queues of 32-stage SRMs that are appropriately triggered during the read/write operations of the NTT, governed by the MAC.

Fig. 13 shows a bit slice of the SRM. We extended the length of the bit slice to 32 stages (32 DFFs). The 32-stage bit-slice design is replicated 32 times to expand to 32 bits, and the incoming trigger signal goes through a FO4-FO4-FO2 fanout tree to provide the trigger to all 32 bits. The outputs are routed to merger-based asynchronous MUXes as illustrated in Fig. 2,12. Since only the appropriate queues are triggered for readout, data input collisions at the merger gates will not happen.

VI-B2 Twiddle Factor CSRM

Twiddle Factor CSRM is a dual-flow clock-based shift register with feedback for circulating Twiddle Factor data. Each PE has two banks: one for standard Twiddle Factor data and one for Twiddle Factor prime data. There are two Twiddle Factor memories: the normal TW storing 32-bit data and the TW prime (TWP) storing 33-bit data. Both memories are CSRM, which keep the data circulating and enable initialization/loading. CSRMs use dual-flow clocking for easier feedback loop completion, and a non-destructive memory (NDRO) controls data loading to prevent data collision and spurious outputs. Data rotates through the CSRM until the NTT operation is completed, with the feedback loop potentially limiting performance. The CSRM size varies by PE, with the stage size for $\text{PE}_{i}$ being $2^{i}$.

VI-B3 Memory Access Controller

The TFF-based counter sets/resets NDROs to generate trigger signals for writing and reading data into coefficient SRMs. The NTT uses a constant-geometry approach with a fixed sequence of read-write access patterns, eliminating the need for random memory access. Traditional FSMs in RSFQ logic face large feedback loop issues, making it challenging to produce control signals at the target clock frequency. Instead, TFF-based counters, arranged in a binary tree as frequency dividers, produce one-hot encoded outputs without feedback loops, only limited by the root TFF gate’s maximum input rate. For $N=128$, increasing the TFF tree stages provides a 128-bit one-hot encoded output, setting/resetting NDROs on specific cycles. Regardless of $N$ (as long as it is a power of 2), the necessary outputs always come from the two leftmost TFFs, allowing pruning of other TFFs.

VI-B4 Glue Logic

We have described the design of the three major components of the memory subblock, namely: (1) the coefficient SRM, (2) the Twiddle factor CSRM, and (3) the MAC. As shown in Fig. 2, several other smaller components still exist to complete the memory subblock. Miscellaneous peripheral circuits that “glue” the memories (SRMs and CSRMs) and MAC together. These include active delay lines for picosecond accuracy timing closure, multistage fanout trees for broadcasting signals, and asynchronous MUXes based on merger trees.

VI-B5 Simulation and Verification

The simulation of the memory subblock for each of the 7 PEs to process $N=128$ coefficients was done primarily at the analog level using JoSIM. Each memory subblock design ranged from 140000 JJs to 190000 JJs. As described in Fig. VI-A and illustrated in Fig. 11, an analog simulation and verification flow was established. We produced appropriate D2F JSON configuration files that generated the same input vectors used in the Python architecture model, following the timing of the signals shown in Fig. 16 at 34 GHz. After the simulation, the waveforms were manually inspected to measure the overall latency and other characteristics. Fig. 17 shows an example waveform used to measure the clk-to-q latency of the memory subblock. The multi-bit output traces were overlaid on each other to illustrate the small output spread achieved.

The VWrap script was configured to create a TOML verification configuration with the corresponding expected outputs obtained from the Python architecture model. All memory subblocks passed analog verification based on the I/O patterns provided by the Python model.

VII Clocking Scheme

SFQ circuits are highly susceptible to timing uncertainty due to process variations and environmental factors, with small logic delays that make them prone to hold violations [30]. In SFQ, a single hold violation can render a circuit inoperable, and stalling the clock does not solve the problem [32]. Inspired by traditional two-phase CMOS clocking, we extended multiphase clocking schemes to create 100% hold-safe circuits where hold violations are resolved by adjusting clock frequencies and phase shifts. This approach uses multiple clocks with the same frequency but shifted phases, significantly reducing the need for path-balancing DFFs and enabling efficient multithreaded operation.

The clock period increases with the number of phases, introducing an area vs. throughput trade-off. For example, using ten clocks reduces the number of DFFs by more than 95% but reduces the maximum throughput by 10x. The reduction in DFFs is achieved by assigning clock phases to gates to resolve path imbalances without DFFs. This synthesis problem is NP-hard, and previous ILP-based solutions did not scale well. We reformulated the multiphase algorithm as a linear program (LP) to improve scalability [33].

We synthesized multiphase clocking versions of our design using this LP formulation, reducing peak performance but ensuring operability regardless of timing variations. We guarantee a satisfactory timing solution post-fabrication using multiphase clocks to drive each gate with a clock phase different from its fanouts. Our designs reduce the DFF cost by 14% using two clock phases at 17GHz (266M NTT/Sec) or by 66% using three clock phases at 8.5GHz (133M NTT/Sec).

VII-A Result and System Verification

Our verification methodology includes verification of the logic behavior of cells, considering the electrical interactions with the interconnects and cells in their fanin and fan-out configurations, followed by the characterization of the cell timing. Verilog behavioral models for the cells were also developed, and the entire design was validated using the Icarus Verilog simulation engine. Despite verifying the logic behavior for each cell independently, as described in [34], potential logic misbehavior can still arise due to cell-to-cell and cell-to-interconnect interactions. Therefore, we have adapted the comprehensive methodology introduced in [34] to ensure that cells account for all electrical interactions within our circuits.

VII-A1 CUS+ generation

In [34], the circuit under study plus (CUS+) is created for verification as follows: Initially, each logic cell in the provided cell library is chosen as the cell under study (CUS). Subsequently, numerous netlists are generated for each CUS, termed CUS+, wherein every logic cell in the library serves as the driver for each CUS input, and each logic cell in the library acts as the load on the CUS output. Additionally, our new SFQ-FHE library includes six interconnection cells, namely 1-2, 1-3, and 1-4 splitters, as well as 2-1, 3-1, and 4-1 mergers. Consequently, for each CUS+ obtained, six distinct versions are created by integrating each of the interconnection cells between each CUS and its driver(s) and load.

In-situ verification

The total number of CUS+ depends on the number of cells in the library and, in our case, reaches $2\times 10^{12}$ configurations. Therefore, it is impractical to verify all possible CUS+ configurations. For a feasible yet thorough method, we perform logic verification only for the CUS+ configurations in our circuit. To further accelerate verification, we skip the CUS+ that occurs only in the memory block since the entire memory block is verified in our SPICE-level simulator, JoSIM. A sample CUS+ is shown in the red block of Fig. 20.

Characterization setup

We use JoSIM with an exhaustive set of patterns. We control the input arrival time and the clock arrival time. We use ideal voltage sources to drive the clock and the input nodes of the CUS. The output node is connected to a PTL, a PTLRX, and a resistance.

VII-B Module function verification

A Verilog model is created for each cell that uses the logic function and delay values obtained from analog simulations. These models are used to verify the entire BU with Verilog simulation. Since the inputs to the BU have a special constraint, we cannot directly apply pure random patterns to the unit. Hence, we have developed a functional pattern generator and a behavioral simulator to compute the corresponding golden result generator for Verilog-based verification. In all our simulations, the waveform output by the Verilog simulator matches the corresponding golden results, establishing the functional correctness of our design as stated in equation 7.

[TABLE]

VII-C Architecture simulator

To verify the proposed memory access pattern, we implemented a software simulator in Python that followed the object-oriented design method. There are two objects in detail: coefficient memory and BU. The number of pipeline stages for each module is specified. These objects are instantiated and connected, as shown in Figure 2.

We first generate multiple NTT operations and store all coefficients inside the list before pushing them into the first PE. The simulation will simulate each module’s inputs and outputs and store the last PE’s valid outputs. Therefore, extra outputs of each module in different clock cycles are needed to help debug the hardware implementation. The golden results are then computed using the brute force method (that is, directly computing the sum of products as shown in Equation (1)) and stored in a list. Finally, the results generated by the last processing element (PE) will be compared with the golden results. We have verified $10^{5}$ test cases and produced the correct results.

VIII Feasibility of FHE

The security of FHE schemes is proven based on ring learning with errors (RLWE) theory. Given a sample $(a,b)$, where $a,b\in R_{q}$, the RLWE theory establishes the difficulty of distinguishing between the following two scenarios.

• •

$a\leftarrow R_{q},s\leftarrow R_{q},e\leftarrow\chi,b=a\times s+e$

• •

$a\leftarrow R_{q},b\leftarrow R_{q}$

where $a\leftarrow R_{q}$ denotes a uniformly random sample $a$ in $R_{q}$, $\chi$ denotes some distribution in $R_{q}$, and $\times$ represents the polynomial multiplication.

The original CKKS scheme [20] is a leveled FHE scheme, where each level corresponds to a specific computation, such as a homomorphic multiplication. The ciphertext modulus at the first level is expressed as $q_{l}=p^{l}\cdot q_{0}$, with $0\leq l\leq L$, $p\approx q_{0}$. Typically, p is a 30-bit prime number. The multiplication level $(l)$ represents the maximum number of homomorphic multiplications performed before the data is corrupted. The result after each level of computation is divided by a scaling factor p to ensure the scheme’s security; errors are intentionally embedded in the least significant bits of coefficients within the ciphertexts. The ciphertext modulus decreases after each computation level to reduce these errors.

The size of the ring, denoted by the degree of the polynomial N, and the bitwidth of the modulus collectively contribute to the security level captured by parameter $\lambda$. A $\lambda$-bit security system requires the attacker to perform $2^{\lambda}$ operations to break it. In the original CKKS scheme, the relation between N, $\log_{2}(q_{L})$, and $\lambda$ is expressed as,

[TABLE]

where P is a special integer generated during the setup phase of the system and is used for homomorphic multiplications only. In addition, the value of P is approximately equal to $q_{L}=p^{L}q_{0}$. Reference [20] sets $N=2^{13}$, $\log(q_{L})=155$, and $\log(p)=30$ to evaluate $x^{16}$ using $\log_{2}(16)=4$ multiplications and to maintain an 80-bits security level.

The original CKKS scheme requires a large bitwidth for the ciphertext modulus to ensure security, increasing the hardware cost. Reference [35] presented the residue number system (RNS) version of the CKKS scheme, where a sizeable large bitwidth modulus is the product of multiple small-bitwidth moduli. Let $\mathcal{B}=\{p_{0},p_{1},p_{2},\cdots,p_{k-1}\}$ denote the basis and $P=\prod_{i=0}^{k-1}p_{i}$. The symbol $[\cdot]_{\mathcal{B}}$ represents the transformation from $\mathbb{Z}_{P}$ to $\prod_{i=0}^{k-1}\mathbb{Z}_{p_{i}}$ where $[a]_{\mathcal{B}}=([a]_{p_{i}})$ with ${0\leq i\leq k-1}$. The ring isomorphism over the integers can be naturally extended to a ring isomorphism $[\cdot]_{\mathcal{B}}$ (i.e., the map: $R_{P}\rightarrow R_{p_{0}}\times R_{p_{1}}\times\cdots R_{p_{k-1}}$) by applying it coefficient-wise over the cyclotomic rings. Consequently, computations can be conducted separately based on these small moduli, leading to a more compact and efficient datapath. Meanwhile, the original ciphertext under the large modulus can be treated as multiple small ciphertexts under the small moduli.

IX Large Scale Implementation

To perform a practical-size NTT operation ($N=2^{14}$) using our proposed hardware, we need to perform two stages of computations, each stage performing 128 SCE-NTT (128-point NTT) for a total of 256 SCE-NTTs, utilizing the divide-and-conquer property. In other words, by employing the proposed NTT-128 architecture, we can execute a $2^{14}$-point NTT operation in $256\times 64=16,384$ clock cycles with appropriate scheduling. Using ideal conditions for the SCE circuit, the clock frequency is limited by the NTT structure. Considering that the NTT-128 operates at 34 GHz, the latency will be 482 ns. In comparison, reference [36] requires approximately 23,894 ns to compute one $2^{14}$-point NTT operation, operating at 300 MHz.

Furthermore, we can leverage the high performance of the proposed design for NTT of any size with the help of additional computation units. For instance, to perform a $2^{15}$-point NTT operation, we may divide it into two sub-problems and then apply the proposed NTT-128 to execute $2^{14}$-point NTT operations. The butterfly operations of the merge step will be performed in the application software. Therefore, the proposed NTT-128 architecture can handle different configurations. For a practical FHE system with a ring size of $2^{14}$ and 60-bit datapath bitwidth, we can apply our proposed SCE NTT-128 design after extending it to the $60$-bit datapath. Based on the divide-and-conquer method, a $2^{14}$-point NTT operation can be divided into $2^{7}$ subproblems, where each subproblem is a $2^{7}$-point NTT.

Meanwhile, the merging of these subproblems is effectively handled by the NTT-128 design. A $2^{14}$-point NTT operation is divided into $14$ stages, each involving $2^{13}$ number of butterfly operations. The NTT-128 design can be employed to execute these butterfly operations across two stages, where each stage comprises $2^{7}$ instances of the SCE NTT-128. This operational flow is illustrated in Figure 21.

Due to the dependency between the first and second stages of the NTT-128 operations, a waiting period of approximately 200 clock cycles is necessary to ensure that all data is flushed from the pipeline registers before one can start the second computation stage. Consequently, the $2^{14}$-point NTT operation requires approximately $(128\times 64\times 2+400\approx 16,784)$ clock cycles. We may instantiate $K$ NTT-128 designs operating in parallel to reduce the cycle counts. In this situation, the total clock cycle count will be approximately $((128\times 64/K)\times 2+400)$ while ignoring clock cycles for the reorder operation to generate correct inputs. However, it is important to consider that increasing the number of SCE NTT-128 cores also increases the required memory bandwidth and complexity of the multiplexer design, leading to a larger area. This approach similarly applies to the inverse NTT operations, where using the inverse NTT-128 module is expected to show comparable performance and hardware requirements as the NTT-128.

For a homomorphic multiplication, two architectures were investigated. First is reusing the same NTT units to perform all NTT operations of homomorphic multiplication operations sequentially [37]. This approach is characterized by a complex data flow and intricate data dependencies, necessitating the deployment of complex finite-state machines and network structures to provide the correct data. In contrast, the architecture demonstrated in [36], pioneered by the Microsoft SEAL team, advocates for instantiating multiple distinct arithmetic units. Each unit is dedicated to a specific step within the homomorphic multiplication process. Therefore, the data rerouting network is simplified, and the throughput of homomorphic multiplication is increased.

We estimated the arithmetic cost of homomorphic multiplication using the proposed design in SCE circuits for different operations (pointwise multiplication and key switch operation) while ignoring the intermediate memory, data reroute network, and finite state machine.

Figure 22 shows a pipelined architecture design that can perform the key switch operation for $N=2^{14}$ and $L+1=8$. All modules are pipelined, and each module is responsible for one operation inside the outer loop of the key switch operation. Computations in different outer loop iterations can be sequentially assigned to the proposed architecture, one after the other.

The $\text{NTT}^{8\times}$ represents that there are eight NTT-128 designs instantiated in the NTT unit for performing $2^{14}$-point NTT operation. The modular multiplication (MM) and modular addition (MA) array comprises multiple modular multipliers and modular adders to perform ”Dyadic Mod” operations. Based on this architecture, we can derive the timing diagram of the key switch operation.

As depicted in Figures 22, our design integrates eight INTT-128 units within the INTT framework, achieving an approximate latency of $2,600$ cycles. Next, we enable performing $L+1=8$ NTT operations within an outer iteration using eight parallel NTT units. Each unit comprises eight NTT-128 modules, aligning its latency with that of the INTT unit. Moreover, we place two modular multipliers at the primary input stage of each NTT-128 unit. These multipliers execute modular multiplications before the NTT operation.

There are $2\times 9$ pointwise multiplications to perform ”Dyadic Mod” operations (ignoring the add operations since the hardware area of modular addition is relatively small.) Consequently, we employ nine MM/MA arrays. Each array is equipped with 14 modular multipliers and adders, capable of performing $2\times 2^{14}$ modular operations. This setup achieves a processing time of approximately $2,400$ cycles. The topmost MM/MA array is designated for the ’Dyadic Mod’ operation, bypassing the NTT process.

After all these intermediate results are stored in memory, we perform the two RNS floor operations via two parallel datapaths. Given that only one NTT-128 design is instantiated to perform the INTT operation, approximately $17,000$ clock cycles are required, as previously discussed. The final stage involves the MM/MA array executing the MS operation. This array comprises roughly eight modular multipliers and 16 modular adders, culminating in a latency of around $2,600$ cycles.

In summary, our proposed architecture, requiring some 90 NTT-128 modules, 302 modular multipliers, and 150 modular adders (under 60-bit datapath), ensures high throughput, enabling the execution of a key switch operation within $20,800$ clock cycles $(2600\times 8)$. Assuming an operational frequency of 34 GHz for the SFQ circuit, the key switch operational throughput is projected to be $(10^{9}/(0.0294\times 20800))=1,634,614$ per second. This throughput significantly surpasses the reference [36], which achieved an approximate throughput of $2,616$ key switch operations per second.

X Conclusion

We have successfully designed and verified a 128-point 32-bit NTT accelerator using superconductor logic that has achieved outstanding results, surpassing CMOS designs by over 100 times, reaching 531M NTT/sec at 34GHz. A new RSFQ cell library featuring 50 cells, including complex multistage compound cells, was developed to achieve this goal. We have ensured the functional correctness and timing of the cells through validation using JOSIM and Verilog. Key components like shift register memory blocks and modular arithmetic units have been designed, validated, and optimized for performance. Our approach to dual-phase clocking has kept the circuits’ high performance while reducing path balancing overhead by 14% and ensuring robustness for hold violations. We have also demonstrated a large-scale implementation architecture for $2^{14}$ points NTT and INTT using the proposed hardware, achieving 1.63 MOP/s, surpassing all other designs. While the current SCE fabrication process does not support such complex circuits, the rapid developments in fabrication will allow the utilization of these circuits in the near future. These achievements underscore the potential of superconducting electronics in high-performance computing and secure communication for the post-quantum era.

Acknowledgments

This work is supported by the Defense Advanced Research Projects Agency (DARPA) under the SCE-NTT: Hardware Accelerator for Homomorphic Computing Utilizing Superconductor Electronics project.