Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS

TL;DR

This paper demonstrates a novel CMOS chip integrating microfluidics and electronics for electrical impedance tomography, enabling picoliter-volume imaging with potential for compact, integrated sensing systems.

Contribution

It introduces the first fully integrated CMOS chip with microfluidics for EIT, combining fabrication, measurement, and off-chip data processing in a compact platform.

Findings

Successful fabrication of microfluidic chambers in CMOS layers

Reconstruction of impedance tomography maps from electrode voltages

Discussion of sources of variation in image reconstruction

Abstract

Electrical impedance tomography with fully integrated microfluidics and electronics is presented for the first time in a CMOS chip. Chambers and electrodes are fabricated in the interconnect layers of a 65 nm CMOS chip through post-processing, enabling picoliter-volumes to be processed and imaged. Tomography maps are reconstructed by reading out voltages from a 16-element electrode array and processing the data off-chip, and sources of variation in reconstruction are discussed. The EIT system presented in this work serves as a proof-of-concept towards using CMOS as a platform for co-integrated microfluidics and electronics.

Full text

I Introduction

Electrical impedance tomography (EIT) is a non-invasive, label-free imaging technique for biological systems [1, 2, 3]. The technique requires the injection of currents and measurement of boundary voltages to reconstruct conductivity maps of the sample, as illustrated in Fig. 1. It has attracted interest for applications like brain and cardiac imaging, probing cell cultures, and even monitoring single-cell behavior due to close links between dielectric properties and physiological state [1, 4]. These applications motivate miniaturizing EIT systems to be compatible with microscale biological environments, with EIT platforms in CMOS potentially offering high electrode densities, simplified packaging and sample confinement, and on-chip processing using integrated electronics [5, 6, 7].

Despite these advantages, miniaturized EIT remains technically challenging, as smaller volumes increase sensitivity to imperfections and impurities [2]. Additionally, the inverse problem of EIT is fundamentally ill-posed, with different forms of regularization necessary to stabilize solutions in state-of-the-art reconstruction algorithms [8]. To address these challenges, we present a fully integrated EIT system in 65 nm CMOS featuring a picoliter-volume microfluidic chamber, digitally reconfigurable electrodes, and circuitry for stimulation and sensing.

II Integrated Microfluidics

The microfluidics described in this work are fully integrated inside the foundry-fabricated CMOS chip. Components are created by selectively etching metal in the interconnect layers of the chip, leaving behind structures made of inter-metal dielectrics (IMDs) [9, 10]. These IMDs largely consist of silicon oxides and nitrides, which are suitable materials for interfacing with biological samples [11]. In prior literature, this subtractive method has primarily been used to integrate photonic circuits within electronic CMOS chips without needing to modify the semiconductor manufacturing process [9]. In this work, we show that this method also enables the fabrication of microfluidic components without the addition of materials like silicon or plastic.

An illustration of the fabrication procedure can be seen in Fig. 2. A standard CMOS chip is designed with passivation covering all metals except those that will be etched. The exposed metals are then wet-etched, with Aluminum Etch Type A being used to remove metals like copper and aluminum and a EDTA/H2O2 mixture used to remove barrier layers like Ta/TaN or Ti/TiN [10]. Finally, the passivation is exposed through laser ablation so that electronic connections can be made to the chip. If electrodes need to be exposed, such as in the case of the EIT system described in this work, laser ablation exposes them as well.

Examples of test-structures fabricated using this method can be seen in Fig. 3. The chambers pictured in Fig. 3a and 3b have a capacity of 4.9 pL, while the chambers in Fig. 3c and 3d have a capacity of 3.3 pL for the upper chamber and a capacity of 20 fL for the inset 3 µm by 3 µm section. Electrodes face the chamber on multiple metal layers from all four sides.

III System Design

The fabricated chip features an integrated EIT chamber and circuits for stimulation, sensing, local oscillator (LO) generation, and digital control. The chamber has lateral dimensions of 150 µm by 150 µm and extends approximately 10 µm below the surface of the chip, with a few metal layers below the chamber left unetched for electrodes and electrical connections. The capacity of the chamber is approximately 225 pL, and a grid of 16 electrodes spans the bottom of the chamber with a fill factor of 66%.

A diagram of the system can be seen in Fig. 4. The clock signal used to operate the digital serial interface is reused to generate the LO through a series of tunable frequency dividers. The LO is applied across a pair of electrodes, and the voltage is then measured at all other electrodes and sent off-chip for processing. EIDORS, an open-source software for modeling EIT, is used for image reconstruction [12]. Multiplexers are used to digitally reconfigure electrode connections for stimulation and sensing.

IV Measurement Results

The EIT chip is fabricated in a 65 nm CMOS process (Fig. 5). The chip is etched with Aluminum Etch Type A at 80∘C to remove copper and EDTA and H2O2 at 50∘C to remove the Ta/TaN barrier bilayer. These etchants are alternated until the microfluidic chamber is fully exposed, and megasonic cleaning is used to clean the chamber in preparation for measurement. The chip operates off of a 1 V supply and consumes 96 to 103 µW for LO frequencies between 500 Hz and 100 kHz, respectively.

The performance of the system is evaluated by inserting glass microspheres in a water-filled chamber and relaying the measured signals to EIDORS for tomography reconstruction. Conductivity maps for a variety of configurations can be seen in Fig. 6, and comparing them to images captured under a microscope indicates strong correlation between microsphere positions and areas of low conductivity. Inaccuracies are largely attributed to the ill-posed nature of the EIT problem and the small volume causing increased sensitivity to impurities in the chamber.

The signal-to-noise ratio (SNR) of the measurement depends on multiple factors, including the exact sample being measured, the location of the sensing electrode with respect to the stimulated electrodes, and the LO frequency. As an example, the SNR varies between 32 dB and 52 dB for the sample configuration depicted in Fig. 6a, with SNR typically increasing with closer proximity between stimulating and sensing electrodes (Fig. 7). We attribute the shape of the histograms primarily to shifts in local temperature and fluid flow in the chamber. An example of variation versus frequency is shown for the sample configuration in Fig. 6b (Fig. 8). These images are fairly similar across frequency, which is expected given that the microspheres maintain a low conductivity versus frequency.

V Conclusion

This work represents, to the best of the authors’ knowledge, the first demonstration of electrical impedance tomography with on-chip microfluidics. A picoliter-scale EIT chamber is fabricated in the interconnect layers of a CMOS chip, and electronics on the same chip interface with the integrated electrodes. Impedance tomography maps are reconstructed from measurements with glass microspheres and compared to micrographs, and sources of variation in reconstruction are discussed. This demonstration illustrates the potential of CMOS as a platform where biology, electronics, and potentially photonics can all interact within the same chip.

Acknowledgment

The authors thank members of the Caltech High-Speed Integrated Circuits group for useful discussions.