Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers

TL;DR

This paper presents a low-bit, systolic array-based hardware accelerator for vision transformers that significantly improves power efficiency and throughput compared to GPUs, enabling more energy-efficient AI inference.

Contribution

The work introduces a specialized systolic array architecture optimized for low-bit integerized vision transformers, enhancing data reuse and reducing communication overhead.

Findings

Achieves 96.83% accuracy on CIFAR-10 with 3-bit model

Delivers 13,568 GOPs/s on FPGA, outperforming GPUs in power efficiency

Offers 1.50x higher throughput and 4.47x better power efficiency than GTX 1080

Abstract

Transformer-based models are becoming more and more intelligent and are revolutionizing a wide range of human tasks. To support their deployment, AI labs offer inference services that consume hundreds of GWh of energy annually and charge users based on the number of tokens processed. Under this cost model, minimizing power consumption and maximizing throughput have become key design goals for the inference hardware. While graphics processing units (GPUs) are commonly used, their flexibility comes at the cost of low operational intensity and limited efficiency, especially under the high query-per-model ratios of modern inference services. In this work, we address these challenges by proposing a low-bit, model-specialized accelerator that strategically selects tasks with high operation (OP) reuse and minimal communication overhead for offloading. Our design incorporates multiple systolic arrays with deep, fine-grained pipelines and array-compatible units that support essential operations in multi-head self-attention (MSA) module. At the accelerator-level, each self-attention (SA) head is pipelined within a single accelerator to increase data reuse and further minimize bandwidth. Our 3-bit integerized model achieves 96.83% accuracy on CIFAR-10 and 77.81% top-1 accuracy on ImageNet. We validate the hardware design on a 16nm FPGA (Alveo U250), where it delivers 13,568 GigaOps/second (GOPs/s) and 219.4 GOPs/s/W. Compared to a same-technology GPU (GTX 1080), our design offers 1.50x higher throughput and 4.47x better power efficiency. Even against a state-of-the-art GPU (RTX 5090), we still achieve 20% better power efficiency despite having 87% lower throughput.

Tables

Table 1. TABLE I: Modules in different operations in SA

	MAC	Post-MAC	Aggregation	Post- aggregation
Q/K	WS	Scale + Bias	Normalization	NormQ
V	WS	Scale + Bias + Quantizer	-	-
A	WS + W-Load	Scale + Exp	Sum	ScaleQ
Av	WS + W-Load	Quantizer	-	-

Table 2. TABLE II: Area and power in module-level and PE-level. The MAC operation dominates both area and power usage in MSA operation. The entire design is limited by the number of LUTs in U250 FPGA

		Module-level				Per-PE
		kLUT	kReg	DSP	Power	LUT	Power
Q	MAC	392.2	343.2	0	6.84	16	0.28
	Norm	11.4	14.1	128	1.39	178	21.8
	NormQ	8.6	17.3	512	2.56	134	40
	Others	7.9	12.2	64	1.53	-	-
	Subtotal	420.1	386.8	704	12.3	-	-
K	MAC	392.2	343.2	0	7.57	16	0.31
	Norm	11.4	14.1	128	1.39	178	21.8
	NormQ	8.6	17.3	512	2.56	134	40
	Others	8.4	14.6	64	1.53	-	-
	Subtotal	420.5	389.2	704	13.1	-	-
V	MAC	392.2	343.3	0	7.30	16	0.30
	Quantizer	2.6	5.1	448	0.45	41	7.00
	Others	1.1	3.3	0	0.00	-	-
	Subtotal	395.9	351.8	448	7.74	-	-
A	MAC	190.1	202.7	0	5.42	15	0.43
	Softmax	35.0	12.3	198	1.98	177	10
	SoftmaxQ	17.8	0.0	0	0.59	90	2.99
	Others	7.0	46.8	7	1.70	-	-
	Subtotal	250.0	261.7	205	9.70	-	-
SA	MAC	202.8	320.2	0	6.30	16	0.50
	Quantizer	3.1	0.0	448	0.13	48	2.00
	Others	12.7	77.0	0	0.00	-	-
	Subtotal	215.5	397.2	0	6.43	-	-
Others		17.2	204.5	0	12.6	-	-
Total (Utilization)		1722 (99.6%)	1991 (58%)	2509 (20%)	61.8	-	-

Table 3. TABLE III: Comparison to other works: We compare our design to other similar works in the ascending order of power efficiency. The derived numbers are labeled with ”*”. Due to the lighter operation (INT3), we achieve the fastest clock and the smallest bandwidth. The systolic array also gives us dense computation, resulting in the high power and the high compute intensity. We also achieve the best power efficiency (GOPs/s/W) among all the transformer accelerator.

	Board	Tech	Model	OP Type	clk (MHz)	Power (W)	Peak GOPs/s	Actual GOPs/s	GOPs/s/W (GOPs/J)	Bandwidth (Read/Write)	OP/Byte
ViA [35]	U50	16nm	Swin-T	FP16	300	39	-	309.6	*7.9	-	-
DFX [36]	U280	16nm	345M (GPT-2)	FP16	-	45	-	184.1	*4.1	400	*0.46
Fan [37]	VCU128	16nm	FABNet	FP16	200	11.4	*128.0	*128.0	*11.3	*$\sim$50	*1.28
Ye [20]	U250	16nm	Rush [38]	INT8	300	77.2	4915	1800	*23.3	12 / 9	*150
Huang[19]	ZCU102	16nm	ViT-T	INT8	300	-	1229	616.1	-	-	-
			ViT-S		300	29.6	1229	762.7	*25.8	-	-
HeatViT [39]	ZCU102	16nm	DeiT-S		-	10.7	-	*221	20.6	-	-
			DeiT-B		-	11.4	-	*425	37.4	-	-
Lu [40]	VU13P	16nm	Transformer (MHA)	INT8	200	16.7	819	*629	37.7	-	-
Ftrans [41]	VCU118	16nm	RoBERTa base	INT16	-	25.1	-	*1077	*43.0	7.88	33.49
Zhang [22]	ZCU9EG	16nm	ViT-S	FP8	300	*21.4	-	*1150	*53.7	-	-
			ViT-B			*21.4	-	*1254	*58.6	-	-
ME-ViT [24]	U200	16nm	ViT-B	INT8	150	17.8	-	*1149	*64.5	*5.74	200
					300	31.8	-	*2298	*72.2	*11.49	200
Calabash [21]	VU9P	16nm	BERT	INT16	243	12.9	*995	880	*68.2	*30.38	28.97
	ZCU102				300	6.6	*614	530	*80.3	*37.5	14.13
Xiao [34]	U250	16nm	Deit-T	Custom INT5	183	40.1		1488	*37.1	-	-
			DeiT-S		192	28.4		2861	*100.8	-	-
			DeiT-B		179	25.3		2332	*92.4	-	-
Auto-ViT-acc[23]	ZCU102	16nm	DeiT-S	FP3.5 +FP4	150	10.3	-	*711	*68.8	-	-
			DeiT-B			11.0	-	*996	*90.3	-	-
			DeiT-S	FP3.5		6.6	-	*689	*105.2	-	-
			DeiT-B			8.1	-	*989	*122.0	-	-
HG-PIPE [33]	ZCU102	16nm	DeiT-T	FP4	375	21.9	-	1974	*90.1	8.53	*231
	VCK190				425	43.4	-	4536	*104.5	8.53	*532
				FP3	425	46.7	-	8898	*190.5	8.53	*1043
			DeiT-S		350	48.1	-	6854	*142.5	8.53	*803
Ours	U250	16nm	3b DeiT-S (MHA)	INT3	400	61.83	42515	13568	219.4	3.13 / 3.13	4342

Table 4. TABLE IV: Latency estimation for the full DeiT-S, where N, H, d, and M are number of words, number of heads, embedding dimension, and MLP scaling, respectively

		Formula	DeiT-T	DeiT-S	DeiT-B
Comm		$3\times N\times d/\left(64\times H\right)$	1782	3564	7128
MSA	SA (6x)	Eqn 15	1729	4297	22963
	Comm	$3\times N\times d/\left(64\times H\right)$	1782	3564	7128
	Projection	$2\times d+N$	582	966	1734
Comm		$3\times N\times d/\left(64\times H\right)$	1782	3564	7128
MLP		$\left(M+2\right)\times d+N$	1350	2502	4806
Comm		$3\times N\times d/\left(64\times H\right)$	1782	3564	7128
Layer (1x)		$4\times comm+$ $MSA+MLP$	10789	22021	58015
Total	Cycles (k)	$12\times$Layer	129.5	264.3	696.2
	Latency ($\mu$s)	12$\times$Layer$\times$2.5	323.7	660.6	1740.5

Table 5. TABLE V: Latency comparison between different works

	Latency ($\mu$s)			GOPs
	DeiT-T	DeiT-S	DeiT-B	DeiT-T	DeiT-S	DeiT-B
Ours (INT3)	324	661	1741	1.23	4.57	17.54
[39] (FP8)	3687	9158	18248	0.75	2.02	7.75
[34] (FP5)	1697	3234	15138	1.23	4.57	17.54

Table 6. TABLE VI: Comparison between DSP-involved and DSP-free design

	Freq (MHz)	Power (W)	BW (GB/s)	Latency ($\mu$s)	TOPs/s	GOPs/W
DSP	400	61.83	3.13	28.56	13.57	219.5
DSP-free	400	96.91	3.13	28.74	13.57	140.0
DSP-free	500	125.5	3.91	22.99	17.37	128.4

Equations

$$[\mathbf{Q},\mathbf{K},\mathbf{V}]={\mathbf{zU}}_{qkv}$$

$$A=\text{softmax}(\tilde{\mathbf{Q}}\cdot {\tilde{\mathbf{K}}}^T/D_h^{1/2})\text{, where }\tilde{\cdot }=LN(\cdot )$$

$$SA(\mathbf{z})=A\mathbf{V}$$

$$MSA(\text{z})=[S{A}_1(\mathbf{z});S{A}_2(\mathbf{z});\dots ;S{A}_k(\mathbf{z})]\cdot {\mathbf{U}}_{msa}$$

$${\mathbf{z}}_l^{\prime }=MSA({\mathbf{z}}_{l-1})+{\mathbf{z}}_{l-1}$$

$$[\mathbf{Q},\mathbf{K},\mathbf{V}]=\hat{\mathbf{z}}{\hat{\mathbf{U}}}_{qkv}=({\mathbf{z}}_{3b}\cdot {\mathbf{I}}_{\Delta z})({\mathbf{U}}_{qkv,3b}\cdot {\mathbf{I}}_{\Delta Umsa})$$

$$[\mathbf{Q},\mathbf{K},\mathbf{V}]$$

$$=({\mathbf{z}}_{3b}\cdot (\overline{\Delta z})\mathbf{I})\cdot ({\mathbf{U}}_{qkv,3b}\cdot {\mathbf{I}}_{\Delta Uqkv})$$

$$=({\mathbf{z}}_{3b}\cdot {\mathbf{U}}_{qkv,3b})\cdot (\overline{\Delta z}\cdot {\mathbf{I}}_{\Delta Uqkv})$$

$$e^x=2^{x\times lo{g}_{2}e}=2^{\lfloor x\times lo{g}_{2}e\rfloor }\times 2^{x\times lo{g}_{2}e-\lfloor x\times lo{g}_{2}e\rfloor }$$

$$2^x\approx \frac{1}{2}x+\frac{1}{2}$$

$$(x-\mu {)}^2\gtrless ((s-\beta )\times (1/\gamma ){)}^2\times {\sigma }^2$$

$$\begin{array}{r}\{\begin{array}{l}{\mu }_i={\mu }_{i-1}+\frac{{\mathbf{x}}_i-{\mu }_{i-1}}{i}\\ {\sigma }_i^2={\sigma }_{i-1}^2+({\mathbf{x}}_i-{\mu }_i)({\mathbf{x}}_i-{\mu }_{i-1})\end{array}\end{array}$$

$$d+3\times \frac{d}{H}+\frac{d}{H}\times (MUL+1)+3\times N+5\times MUL+24$$

$$Latenc{y}_H=Latenc{y}_1+(H-1)\times Throughput$$

$$max(N+d,d/H+2N,(3\times N\times d)/(64\times H))$$

$$\begin{array}{r}\{\begin{array}{l}{\mu }_i={\mu }_{i-1}+[(2^{\nu }/i)(s\times x_i-{\mu }_{i-1})]/2^{\nu }\\ {\sigma }_i^2={\sigma }_{i-1}^2+(s\times x_i-{\mu }_{i-1})(s\times x_i-{\mu }_i)\end{array}\end{array}$$

$$\text{Power}\propto \text{OPs}\times (\text{bitwidth}/8{)}^2$$

$$\begin{array}{r}\{\begin{array}{l}\text{Throughput}\propto f\times \text{Density}\times \text{Die size}\\ \text{Power efficiency}\propto \text{GOPs}/\text{J}\approx 1/({\text{C}}_g{\text{V}}^2)\end{array}\end{array}$$

Full text

In this work, we address these challenges by proposing a low-bit, model-specialized accelerator that strategically selects tasks with high operation (OP) reuse and minimal communication overhead for offloading. Our design incorporates multiple systolic arrays with deep, fine-grained pipelines and array-compatible units that support essential operations in multi-head self-attention (MSA) module. At the accelerator-level, each self-attention (SA) head is pipelined within a single accelerator to increase data reuse and further minimize bandwidth.

Our 3-bit integerized model achieves 96.83% accuracy on CIFAR-10 and 77.81% top-1 accuracy on ImageNet. We validate the hardware design on a 16nm FPGA (Alveo U250), where it delivers 13,568 GigaOps/second (GOPs/s) and 219.4 GOPs/s/W. Compared to a same-technology GPU (GTX 1080), our design offers 1.50x higher throughput and 4.47x better power efficiency. Even against a state-of-the-art GPU (RTX 5090), we still achieve 20% better power efficiency despite having 87% lower throughput.

Ching-Yi Lin$\dagger$ and Sahil Shah$\dagger$

I Introduction

Recent advancements in large language models (LLMs) have enabled them to achieve performance across a wide range of human tasks. To support their deployment, frontier AI laboratories offer inference services with hundreds of GWh of energy annually [1]. For example, OpenAI reportedly spends $4 billion on running inference workload alone [2]. At the same time, such services typically charge users based on the number of tokens processed. Under this cost model, minimizing power consumption and maximizing throughput have become key design goals for the inference hardware. These two metrics are often combined into a single metric token/s/W in model performance evaluation [3].

Currently, GPUs are the predominant computing platforms employed by service providers. These hardware solutions offer high bandwidth and flexible programmability to accommodate a wide variety of machine learning models. However, this flexibility becomes less advantageous in LLM inference server due to modern huge query-per-model ratio over the lifetime of the model [4]. In other words, with the vast number of inference requests for the same model, it is worthwhile to explore hardware specialized for a particular model for superior throughput and power efficiency.

Based on these considerations, the primary design goal for service-oriented hardware is to build a more model-customized architecture to leverage model-specific characteristics. Specifically, we focus on increasing compute density and throughput within a low-bandwidth environment for a more scalable infrastructure. To meet these goals, model integerization has emerged as a promising strategy  [5, 6, 7] to achieve both subgoals using lightweight integer arithmetic. Prior researches have shown that convolutional models can be quantized to 8-bit without observable accuracy loss ($<1\%$ top-1 accuracy on ImageNet) [5] while still being compatible with mobile platforms. Nevertheless, their latency is not improved due to the limited improvement of their INT8 logic [5]. In this work, we focus on low-bit networks ($\leq$4-bit), which provide superior hardware performance than 8-bit. While this comes with a slight reduction in model accuracy, this inherent tradeoff between accuracy and hardware cost aligns well with the diverse accuracy-cost options offered by frontier AI labs. We specifically select 3-bit as our target precision, because prior work has demonstrated that a 3-bit quantized DeiT-S incurs only a 1% loss compared to the full-precision DeiT-S on the ImageNet dataset [8]. Following the integerization approach [6], we build an integerized model where compute-intensive modules are realized in low-bit integer arithmetic

Despite the clear benefits and successful low-bit integerization, the efficient inference of low-bit model remains a challenge. To build a high-throughput, low-bandwidth, and power-efficient architecture, we analyze both FPGA- and GPU-based hardware built in the same technology (16nm.) As the roofline model [9] illustrated in Figure 1, recent FPGA works align with PCIe 3.0 x8, which is the most common interface protocol for FPGAs. This alignment implies that the throughput of these designs is constrained by low operational intensity, which usually arises from the poor OP reuse in small-size operations to support a wide range of model. In this work, our design leverage model-specific properties of the target application to strategically select the tasks with maximized OP reuse and low communication overhead for offloading. Furthermore, the simpler logic from low-bit arithmetic results in fewer gates per multiply-accumulate (MAC), leading to higher compute density and the ability to perform more operations from a received packet.

To achieve these aforementioned goals, we propose a systolic array-based architecture with a deep and fine-grained pipeline that support massive parallelism and high clock frequencies. The systolic array template includes support for aggregation operations such as layer normalization and softmax via array-compatible units, ensuring the template can be generalized to various models. To handle the cycle mismatch between arrays, we employ FIFOs to eliminate the need for cache or random memory access during the inference.

Our main contributions are summarized as follows:

• •

We propose a systolic array-based architecture for low-bit MSA, specifically optimized for operational intensity to achieve high throughput under the low bandwidth constraints.

• •

We design systolic array-compatible Softmax and Layer Normalization modules, allowing these aggregate operations to seamlessly integrate with our systolic array template.

• •

We optimize the power efficiency of the system through low-bit arithmetic and accelerator pipelining, surpassing state-of-the-art FPGA implementations.

• •

We conduct a detailed analysis for power and area, demonstrating that the MAC operations primarily dominate power and area of this MSA accelerator.

II Background

II-A Model Quantization

Low storage and efficient arithmetic are two critical design objectives for ML model inference. Methods to reduce the model storage size generally fall into two categories. In the first category, often termed model compression, aims to minimize model size but preserving the same accuracy. This method includes pruning the unused connection [10] or incorporating information entropy in loss term during training[11].

The other category focuses on training inherently low-information networks instead of reducing from high-precision models. Examples include Binarized Neural Network [12] and XNOR-Net [13], which constrain the model weights and activations to $\{-1,1\}$. While Ternary Neural Network [14] expands the quantized space to $\{-1,0,1\}$, the accuracy of these models are low ($<$90% in CIFAR-10) due to their small information space in the model. To enable more generic low-information networks, DoReFa-Net [15] achieved arbitrary-bit weight and activation using a straight-through estimator (STE). Choi [16] further improved accuracy by employing statistics-aware weight binning (SAWB) and parameterized clipping activation (PACT), achieving over $74.2\%$ ImageNet accuracy with ResNet50.

For transformer-based models, FQ-ViT [17] reduced DeiT series models to $4$-bit attention map and $8$-bit weights within $2$% accuracy loss. Q-ViT further pushed model precision to 3-bit with similar accuracy using switchable scale [8]. Despite the impressive accuracy and reduced storage space of these quantized models, they still require dequantized operands during the inference, which not only introduces computational overhead, but also makes the computational-intensive modules, such as linear layer and matrix multiplication, operate in high precision [7].

To achieve both low storage and efficient arithmetic simultaneously, integerized model have emerged as a widely studied solution to leverage the maturity of integer-arithmetic.

Jacob el al. [5] first quantized MobileNet to 8-bit and achieved only $1-2\%$ accuracy loss on ImageNet. For transformer-based model, I-BERT [18] adopts polynomial approximation for Softmax and GeLU functions. I-ViT [7] further enhanced the performance using shift-based Softmax and GeLU. Huang [19] applied shift-based exponential and second-order polynomial approximation for improved hardware performance. Despite these advancements in integerized models, a critical gap remains between the 8-bit model integerization and a low-bit, efficient implementation. In this work, we propose a low-bit quantized model following a low-bit integerization algorithm [6]. Our method builds on the success of low-bit quantization and model finetuning by training an integerized model from a quantized model checkpoint, enabling both high accuracy and efficient inference

II-B Systolic Array

Systolic arrays are renowned for their inherent parallelism and pipelined dataflow, making them ideal for achieving high throughput and low memory bandwidth requirements. However, their highly regular structure often limits their flexibility when adapting to the diverse compute graphs of various models.

The design of systolic arrays typically focuses on two optimization goals. The first is to maximize the utilization rate of processing elements (PEs). While some efforts have increased utilization rate by parallelizing multiple operation within a single PE [20, 19], the utilization rate remains bounded by the complicated and varied operations in convolutional or transformer networks. Building on this, Calabash [21] improved the utilization rate at the module-level by multiplexing systolic arrays, enabling different operations through reconfigurable configurations. At the PE-level, Zhang employed weight-loop computing unit (WLCU) with a bubble-free dataflow to maximize the utilization rate [22]. In addition to customized flow, high-level synthesis (HLS) tools are also used to optimize the performance [23, 20].

The second design goal is to increase the operational intensity by maximizing reuse and translate it into higher throughput from a given bandwidth [24]. For example, Eyeriss [25] proposed row-stationary dataflow and utilized local scratchpad memories to maintain the model parameter locally and reduce data transfers. Similarly, in transformer-based model, ME-ViT [24] also introduced a single-load policy to buffer weights and intermediate data to minimize external data traffic.

In this work, we focus on the second goal to optimize the operational intensity. We exploit the regular architecture from transformer models to select high-operational-intensity cut point. This minimizes off-chip traffic and enables us to achieve operational intensity higher than 4000 OPs/byte.

III Integerized Model

III-A Visual Transformer (ViT) Overview

DeiT model, the target model in this work, consists of MSA and feed-forward network (FFN), as illustrated in Figure 2. The difference between Figure 2 and ViT [26] is the extra distillation token at the input. Our accelerator design focuses on the MSA module, as it contains linear layer, matrix multiplication, Softmax, and layer normalization, covering all the operations in FFN except for an element-wise non-linear function GeLU.

Built from single SA, the SA result can be obtained from input projection (Eq. 1), getting attention score (Eq. 3), and dot-product attention (Eq. 3).

[TABLE]

[TABLE]

[TABLE]

Here we follow the expression in ViT [26] with $\cdot$ operator explicitly for matrix multiplication. The difference is the additional layer normalization in Equation 3. The post-normalized model has been shown to achieve high data efficiency in several applications [27]. The results from multiple SA modules are concatenated to obtain MSA results as in Equation 4.

[TABLE]

[TABLE]

To reduce the parameter size, Q-ViT approximates $\mathbf{Q}$, $\mathbf{K}$, $\mathbf{V}$, $A$, and $SA_{i}(\mathbf{z})$ in a low-bit expression [8]. A low-bit dequantzied expression $\hat{\mathbf{z}}$ can be approximated as the product of low-bit integer $\mathbf{z}_{3b}$ and a channel-wise step size $\Delta_{z}$. This step size is shared across all data in the same channel. The dequantization can be obtained in a matrix multiplication form $\mathbf{z}_{3b}\cdot\mathbf{I}_{\Delta z}$, making input projection of the MSA be expressed as

[TABLE]

Although this quantization method can reduce the storage size, the operands of matrix multiplication $\mathbf{z}_{3b}\cdot\mathbf{I}_{\Delta z}$ and $\mathbf{U}_{qkv,3b}\cdot\mathbf{I}_{\Delta Umsa}$ are still floating point. This results in high computational use due to the square relationship between the number of gate and the bit [28].

To reduce the computational resource, we aim to factor out the step size and separate the matrix multiplication to a low-bit integerized matrix multiplication $\mathbf{z}_{3b}\cdot\mathbf{U}_{qkv,3b}$ with a post-dequantization. To achieve this, we reduce the channel-wise $\Delta_{z}$ to the global step size $\overline{\Delta z}$ to allow it to be factored out. The integerized matrix multiplication is expressed in Equation 9

[TABLE]

The integerization technique can be applied to other operations, such as getting attention score and dot-product attention. Figure 3 shows the original compute graph and the integerized compute graph. To emphasize the effectiveness of the integerization, the low-bit data and the integer computation are highlighted in red. In the integerized compute graph, the compute-intensive modules, linear layer (Linear) and matrix multiplication (Matmul), are executed in low bit. Although normalization and softmax are still full precision, these modules have lower complexity ($O(N^{2})$) than Linear and Matmul ($O(N^{3})$).

III-B SA Offloading

To maximize the operational intensity (OP/byte), the offloaded operation needs to (1) Minimize the size of the input/output (2) Maximize the data reuse.

To maximize the data reuse, the operation needs to include the compute-intensive operations. In MSA, there are multiple SA modules and a linear module. Each SA includes two matrix multiplication and one linear module. As the ability to accommodate all these modules depends on the number of resources and device/technology dependent. We leave the problem until the implementation stage.

Figure 4 shows the data size at each stage in SA to analyze their communication load. $\mathbf{z}$ is stored until it is used in final addition (Equation 5), and the quantized copy is used to generate MSA result. The quantized $\mathbf{z}$, or $\mathbf{z}_{3b}$, is fed into FPGA due to its small size (28kB in DeiT-S). Similarly, the $SA_{3b}(\mathbf{z})$ is returned from the FPGA. One noting thing is, although the $MSA(\mathbf{z})$ is integerized to $([SA_{3b,1}(\mathbf{z});\cdot;SA_{3b,k}(\mathbf{z})]\cdot\mathbf{U}_{3b,msa})\cdot((\overline{\Delta_{SA}})\mathbf{I}_{\Delta Umsa})$, and the $SA_{3b}(\mathbf{z})$ is sent from the FPGA, other operations, including the concatenation, low-bit matrix multiplication, and dequantization, are all performed on the host side to save communication bandwidth.

IV Accelerator Architecture

IV-A Dataflow Overview

The high-level dataflow is illustrated in Figure 5. The accelerator receives input from a host-side quantizer, which converts the full-precision $\mathbf{z}$ into low-bit values $\mathbf{z}_{3b}$. These low-bit values are then sent to three systolic arrays to generate $\mathbf{Q}_{3b}$, $\mathbf{K}_{3b}$, and $\mathbf{V}_{3b}$ respectively. Some systolic array includes an additional module for aggregation operation such as normalization or softmax.

To reduce model-to-model communication overhead, all the high-precision data and intermediate results are both within individual modules. In the other words, only low-bit data are transmitted in the inter-module connection, or the black and gray lines in the accelerator in Figure 5. This reduces place-and-route efforts or simplifies further application-specific integrated circuit (ASIC) implementation.

IV-B Array Design

Figure 6 illustrates the architecture template. The array consists of a 2D MAC array, a post-MAC array, a systolic aggregation module, a triangular delay unit, and a post-aggregation array. The 2D MAC array performs the matrix multiplication $\mathbf{W}^{T}\mathbf{X}$ in a weight-stationary (WS) dataflow. The results are then processed by the post-MAC units. Next, the aggregation module performs row-wise aggregation on the post-MAC module output $f(\mathbf{W}^{T}\mathbf{X})$, and the aggregation results are propagated to post-aggregation module in a systolic manner. A major advantage of this architecture is its fully systolic nature: all inter-PE communication is local, short-range, and avoids costly broadcast transmission in data. This matches our aforementioned design goal to reduce the bandwidth requirement.

Despite the simple template, this architecture is general enough to support all the operation in MSA, including scaling, quantization, layer normalization, and softmax. The following sections provide a detailed breakdown of each module.

IV-B1 Processing Elements (PE) in MAC Array

The MAC array aims to perform the matrix multiplication $\mathbf{W}^{T}\mathbf{X}$ in a WS dataflow. Each PE is a 3-bit MAC unit, executing $sum_{i,j}\leftarrow x_{i,j}\times w+sum_{i-1,j}$ and $x_{i,j}\leftarrow x_{i,j-1}$. The $x_{i,j}$ and $sum_{i,j}$ are propagated rightward and downward, respectively. In addition to MAC operation, some operations in ViT, such as quantization or biasing after the MAC stage, require post-MAC arithmetic. These can be efficiently handled by appending element-wise PE at the output of the MAC array. Since the dataflow timing is preserved, these modules can operate seamlessly without requiring additional timing-matching modules.

IV-B2 1D Systolic Aggregate Operation

Unlike convolutional neural networks, ViTs often require aggregation operation like layer normalization or softmax in MSA layers. These operations compute values across channels (e.g. mean, variance, or exponential sum). To keep high throughput, we implement these aggregation modules using a systolic-based manner.

As shown in Figure 7(A), each aggregation PE combines its input with the accumulated result from previous (left) PE and passes to the next (right) PE. Once the aggregation completes, the aggregation result is propagated back to the post-aggregation module for further processing.

Timing alignment across channels is critical for systolic compatibility. Figure 7(B) visualizes the timing of the aggregation: Data from each channel is delayed by one cycle relative to its previous (left) neighbor, matching the timing of the MAC array. This enable us to place one-cycle aggregation PEs in a systolic row without additional delay modules at the input. However, the post-aggregation modules receive the aggregation result at staggered times and and therefore require timing alignment.

To address the timing alignment between aggregation and post-aggregation module, we introduce a triangular delay module, named after its arithmetic sequence in the number of delay. This module ensures the aggregation result can be fed cycle-by-cycle in a backward order (right-to-left). An alternative design choice would be to broadcast the aggregation result in a forward order, same as the aggregation dataflow. However, this only changes the triangular delay into a parallelogram delay, which has the same cumulative delay and may further reduce the clock frequency due to longer transmission path.

Figure 7(C) demonstrates an example how softmax quantization is implemented in this structure: The MAC output $\mathbf{X}_{i}$ is first processed by a multi-cycle exponential unit to obtain $e^{\mathbf{x}_{i}}$. The aggregation module then sums these exponentials and propagate the partial sums to $e^{\mathbf{X}_{i}}$ to compute the final $\Sigma e^{\mathbf{X}_{i}}$, which is propagated to all post-aggregation units again. Each post-aggregation unit then quantizes its input using a dynamic-scaled step size $\Delta_{i}\times\Sigma e^{\mathbf{x}_{i}}$ to achieve $q_{\Delta_{i}}(e^{\mathbf{X}_{i}}/\sum_{i}e^{\mathbf{X}_{i}})$. This example illustrates how complex operations can be decomposed across post-MAC, aggregation, and post-aggregation units. The details of quantizer and other modules will be discussed later in Sec. IV-C.

The aggregation module improves the throughput by pipelining aggregation operation over multiple cycles. However, it increases the latency due to additional cycles required in inference. This additional latency cycles is proportional to the number of channels (typically ranges from 50 to 200). In our implementation, each normalization takes extra $64$ (cycle) $\times 2.5$ (ns) $=160$ (ns), which is only about $1.7\%$ of total latency. Given our throughput-centric design goals, this is an acceptable tradeoff to sustain a $400$MHz clock in our design. In contrast to latency-effected aggregation modules, post-MAC and post-aggregation modules are purely element-wise and can be executed in parallel without impacting latency, as long as the operands are available.

IV-C Operation Mapping

In earlier sections, we introduced the template architecture for our systolic array. Table I summarizes the required modules within the systolic array to support various operations in a ViT model. In this section, we elabroate on how each operation is mapped to the hardware architecture.

IV-C1 Weight-stationary Dataflow for Matrix Multiplication

General Matrix multiplication (GeMM) acceleration has been widely studied for decades, with various architectures and dataflow proposed [21, 25]. The choice of dataflow often depends on the target use cases and performance priorities.

As this work focuses on high-throughput applications, the design only uses systolic-based weight feeding and local connection. We deliberately exclude multicast-based or broadcast-based networks in data transmission to avoid communication bottleneck. Figure 8 compares WS and output-stationary (OS) dataflow. In systolic-based architecture, both dataflow achieve the same completion time, indicating equal throughput at the system level. Our preference for WS stems from its structural similarity to the linear layers.

IV-C2 Weight Loading Unit for Matrix Multiplication

Unlike linear layers, where weights remain static and can be preloaded before the inference, dynamic matrix multiplication requires loading weights with high throughput. To meet this requirements, we introduce a dedicated weight loading unit.

As illustrated in Figure 9(A), the weight loading unit consists of a shift register and a series of latches connected to intermediate registers. Each latch feeds its output into a MAC unit as the corresponding weight.

Figure 9(B) shows the behavior and timing diagram of this unit. Weights are serially input into the shift register, forming a parallelogram pattern with the same (color-coded) value propagating diagonally. Once the enable signal is triggered, the values in the shift register are latched and held by the latches. This content-holding creates a rectangular pattern until the next enable is received.

IV-C3 Quantizer Design

The quantizer module converts high-precision data from a systolic array into low-precision values for inter-module communication. In the simplest form, it rounds the full-precision input $x$ to an integer with step size $\Delta_{x}$, i.e., $\lceil x/\Delta_{x}\rfloor$, with the $\lceil\cdot\rfloor$ a rounding function.

Given our use of 3-bit quantization, we implement $2^{3}-1=7$ comparators in parallel comparing the input with 7 thresholds $\Delta_{x,i}=(i+\frac{1}{2})\Delta_{x}$, denoted as $x\lessgtr\Delta_{x,i}$, for $i=0,1,\dots,6$. Each boolean comparator results are combined to a 3-bit integer as the quantizer output.

We also implement several quantizer variants for more complex cases. For example, the ScaleQ used in Figure 7(C) supports $x\lessgtr s\times\Delta_{x}$, where $s$ is provided by another module. This enables combined softmax and quantization operations, by setting $x=exp(\mathbf{z}_{i})$ and $s=\Sigma_{i}exp(\mathbf{z}_{i})$

IV-C4 Exponential module

Exponential operation is widely used and has been approximated in various works [8, 18, 19, 7, 24]. Most approaches rely on the following decomposition

[TABLE]

The first term $2^{\lfloor x\times log_{2}e\rfloor}$, can be implemented efficiently with bit shift. The second term, which lies in range $(-1,0]$, is approximated in various ways, ranging from first-order [8], second-order [18, 19], to shift-based [7]. In our design, we adopt a first-order approximation, namely

[TABLE]

As the approximation in Equation 10 is exact in $x=-1$ and $x=0$, we use it to linearly approximate the power-2 with the range $(-1,0]$. Our experiments showed that the more complex approximations did not significantly improve the accuracy.

The implementation is illustrated in Figure 7 (C): The prescaled ($1024$x) input is multiplied by $log_{2}e$. The most significant bits are used for the shift, while the remaining bits approximate $2^{x}$ as in Equation 11. The half-scaling and addition of Equation 11 can be implemented by 1-bit right shift and single-bit overwrite. Then the approximation is passed to the shifter for the final result (Equation 10).

It’s also worth noting that the exponential results are used in softmax as $softmax(x)=e^{x}/\Sigma e^{x}$. Since this result is normalized and the scaling factors cancel out, there is no need to undo the initial prescaling.

IV-C5 Layer Normalization + Quantization

Layer normalization is one of the most complex operation in ViT pipeline. To compute $q_{\Delta S}(\gamma\times(x-\mu)/\sigma+\beta)$, the first challenge lies in the division and square root in variance $\sigma^{2}$. This can be solved by algebra tricks [6], which results in a two-stage logic in Figure 10(A): The first stage performs the comparison

[TABLE]

and extracts the sign of $x-\mu$ and $(s-\beta)/\gamma$, and the second stage combines the comparator results and the sign to the correct output. We do not report the detailed derivation about this logic but this can be derived from K-map.

The second difficulty is to compute the $\mu$ and $\sigma^{2}$ computation in a systolic-friendly manner. We use Welford’s algorithm [29] to compute $\mu$ and $\sigma^{2}$ in an online manner following

[TABLE]

with initial condition $\mu_{0}=0$ and $\sigma^{2}_{0}=0$. Equation 13 relies on current input $\mathbf{x}_{i}$ and the previous mean $\mu_{i-1}$ and variance $\sigma^{2}_{i-1}$ to calculate current mean $\mu_{i}$ and variance $\sigma^{2}_{i-1}$, making them well-suited to a systolic implementation. The aggregation module is shown in Figure 10(B)

The output of the online statistics module is sent to the NormQ module, illustrated in Figure 10(C). NormQ module performs the division-free and square root-free quantizer based on Equation 12, using pre-computed parameter $(s-\beta)^{2}/\gamma^{2}$ and $(s-\beta)/\gamma$. Functionally, the first stage NormQ behaves like a ScaleQ quantizer with input $(x-\mu)^{2}$, scale $\sigma^{2}$, step size $(s-\beta)^{2}/\gamma^{2}$. Two boolean sign signal $x-\mu>0$ and $(s-\beta)/\gamma>0$ are combined via logic gates to determine the final output.

IV-D Accelerator Pipelining

The proposed architecture implements a SA module for ViT. A straightforward approach to executing MSA is to parallelize SA accelerators, with each one dedicated to processing a single SA and storing its parameter, as illustrated in Figure 11(A). In this configuration, the accelerators can be daisy-chained to reduce communication bandwidth. However, this implementation requires a large number of resources ($>$10M LUT) and cannot fit most commercial FPGAs.

Although our design support extension to multi-FPGA due to our low communication bandwidth, we also provide accelerator pipelining to fit all SA operations into a single accelerator.

Figure 11(B) demonstrates the pipelined accelerator idea: The input is selected either from external data source or reused from previous inputs through an input selector. The accelerator maintains the parameters for all SA heads and switches between them as needed. Pipelining accelerator does not increase the latency compared to our daisy-chain baseline. However, the throughput is reduced because the next input (yellow) has to wait until the current input (red) has been processed by all SA stages. In the case of DeiT-S ($H=6$), this results in a 6 times slower throughput. This provides a tradeoff between number of resources (or area) and throughput.

Another benefit of this pipelining technique is smaller bandwidth. As each input remains active in the accelerator for a longer time, the same data can be transmitted over a longer period. This effectively reduces the bandwidth requirement by $H$ times for the pipelining technique.

Pipelining accelerator is especially beneficial for FPGA-based system because most commercial FPGAs provide fast computational modules and plenty of DSPs, but only few FPGAs support high-speed interface such as HBM. This observation also aligns with recent trends in ASIC about the growing compute-to-communication ratio [30]. With operation-level pipelining, our approach provides a tradeoff between communication bandwidth, area, and throughput in inference accelerators.

V Results

V-A Models and Training Details

We evaluate our experiments using ImageNet. Prior work has demonstrated that quantizing a pretrained model often yields higher accuracy than training from scratch [26]. For ImageNet experiments, we leverage a pretrained quantized model [8] on ImageNet. The difference between the quantized model and our integerized model is the per-channel and the global step size. Thus, we initialize our model with the pretrained parameter used in quantized model, and finetune for only 20 epochs with learning rate 1e-5 and Adam optimizer.

V-B Experimental Setup

To validate our hardware design, we implement the proposed system on the AMD Alveo™ U250 Data Center Accelerator FPGA, which is based on 16nm FinFET technology. We synthesize our design using Vivado 2024.2. Our implementation includes a pipelined accelerator with an on-FPGA PCIe communication module. In the following section, we report performance metrics such as timing, power, and area number from the synthesis report. While more detailed analysis methods are available, we consider the synthesis results sufficiently accurate and representative for validation purposes.

V-C Timing Performance

The two most important metrics in timing are latency and throughput. As our design is based on a cycle-based pipeline, both metrics can be analytically derived from the timing diagram.

Figure 12 shows the timing diagram of an SA operation. After the input is transmitted, the $d$-channel $\mathbf{z}$ enters the array in a systolic dataflow, showing a parallelogram in the timing diagram. Then the post-MAC result ($\mathbf{z}\mathbf{U}_{k}$) and normalized low-bit key ($\mathbf{K}_{3b}$) are generated. The $\mathbf{K}_{3b}$ is later reordered from systolic order to parallel order in preparation for the first matrix multiplication ($\mathbf{QK^{T}}$), where it serves as the weight. This matrix $\mathbf{QK^{T}}$ is later passed through softmax and quantization module to produce $A$, which is finally used in the second matrix multiplication to compute the SA result $A^{T}\mathbf{V}$.

V-C1 Communication-Free case

We begin by analyzing a simplified communication-free case with single SA unit. Shown in Figure 12, the throughput of a single SA depends on two factors: (1) the length of systolic input $\mathbf{z}$ (2) the total duration the $\mathbf{K}_{3b}$ must be held in the weight loading unit. The former spans $N+d$ cycles, while the latter must hold $\mathbf{K}_{3b}$ from the start of the $\mathbf{Q}$ input until the end of matrix multiplication $\mathbf{QK}^{T}$, totally $d/H+N+N$ cycles.

In DeiT-S ($N=198$, $d=384$, and $H=6$), the total interval between tokens (or ”pitch”) is $max(N+d,d/H+2N)=582$ (cycles). This can be translated to $1.46\mu s$/token or $684.9$ million tokens per second, in this ideal scenario.

The latency of this communication-free, single SA operation, from the first bit of $\mathbf{z}$ to the final bit of $A\mathbf{V}$, can be computed analytically in the unit of cycles as

[TABLE]

Here we alias $MUL$ as the number of cycles for multipliers. On the U250 FPGA, $MUL$ equals $1$, since each full-precision multiplication fits in a single DSP48E2 unit. For later DSP-free implementation, this value may increase due to multi-cycle multiplication.

Using Equation 14 above, a single SA module in DeiT-S takes $1,327$ cycles. To scale this up to all heads in a MSA module, the total communication-free latency becomes

[TABLE]

Using the number obtained above, we get the communication-free MSA latency $1327+(6-1)\times 460=3627$ cycles.

V-C2 Communication-Aware case

To include communication effects, we first estimate the total data transfer time. For a 64-bit/cycle bus, the transmission time for the entire MSA input is $(3\times N\times d)/64=3564$ cycles.

Accelerator pipelining allows this communication to be amortized across $H$ heads. For DeiT-S, the effective time for communication per head is $3564/6=594$ cycles. Combining with the analysis in communication-free, the actual interval, or $1/$throughput, becomes

[TABLE]

Our design, being communication-bound, has an interval of $(3\times N\times d)/(64\times H))=594$ cycles. Running at $400$MHz, this implies a communication bandwidth $64$ (bit/cycle) $\times 400$(MHz)$=3.125$(GB/s), and a throughput $1.49\mu s$/token or $673.4$ million tokens per second.

To compute full latency, we add the communication costs to communication-free latency which results in $1327+(6-1)\times 594+3564\times 2=11425$ cycles or $35.63$($\mu$s) under $400$MHz clock. This summation is valid because the communication time ($3564$) is smaller than the computation time ($1327+(6-1)\times 594$), allowing communication of the current MSA to overlap with the computation of the previous MSA while avoiding pipeline bubbles.

V-D Power analysis

The total power consumption of our design is 61.83 (W), with a detailed breakdown shown in Figure 13. This breakdown categorized the power into five primary operations ($\mathbf{Q}$, $\mathbf{K}$, $\mathbf{V}$, $A$, and $A\mathbf{V}$), along with supporting periphery (input selection/delay, parameter feeding, and others) and static device power.

The breakdown shows that the 2D MAC array power accounts for the majority of the power consumption across all primary operations. Among these, the least dominant one is the $A$. This is primarily due to its complicated post-MAC operations using shifter-based exponential computations, and relatively large portion of post-MAC PEs; specifically one post-MAC PE every $d/H=64$ 3b-MAC PEs.

In contrast to the power dominance of the MAC array, quantization and other post-MAC operations contribute only a small portion to the overall power. Although these units consume more power per PE, their total contribution remain limited due to the lower number of PEs. This observation validates the idea of our design strategy, which concentrates optimization efforts on the compute-intensive modules.

Beyond the module-level view, we also perform a detailed analysis at the PE-level. Table II reports the per-PE power consumption for various modules. The 3-b MAC PE in linear layers ($\mathbf{Q}$, $\mathbf{K}$, and $\mathbf{V}$) consume $0.28-0.31$W per PE, while PE in matrix multiplication consumes more power, ranging from $0.43-0.50$W per PE. The increased power is attributed to the additional weight loading unit in matrix multiplication array.

V-E Area analysis

To demonstrate the area efficiency of our integer-based design, we also report hardware resource usage. Table II presents the number of look-up tables (LUTs), registers, and DSPs used across different modules. At the first glance, it is evident that our design is limited by LUT availability. Then, similar to the power analysis, the MAC array also dominates in terms of area utilization. In fact, the MAC array’s dominance in area is even more pronounced than its dominance in power.

We also examine area at the PE-level to estimate the theoretical performance. The 3-b MAC PE, whether used in either linear layers or matrix multiplication, takes between $15$ to $16$ LUTs per PE. The slight discrepancy between the actual and projected ($16\times$ number of PE) module-level LUT count arises from reduced partial sum bitwidth in the first few rows of the MAC array. Additionally, we find the extra weight loading unit in PEs of matrix multiplication do not use any LUT except for the global enable.

The average $15.87$ LUTs per MAC PE sets an upper bound for the scalability on a single FPGA. Given a total $1,728,000$ LUTs on U250, the maximum number of 3-b MAC PE can be derived from $1,728,000/15.87=108,885$. In our design, we implement $3\times 384\times 64+2\times 64\times 198=99,072$ PEs, which occupies about $90.9\%$ of the total LUT resources.

V-F Error Analysis

Since the accuracy of 3-bit quantized DeiT-S has been reported compared to full-precision DeiT-S [8], our analysis focuses on the accuracy gap between the 3-bit quantized DeiT-S [8] and our 3-bit integerized DeiT-S.

Most of our integerization process is algebraic equivalent to the quantized model, which means the results should be identical under the assumption of infinite precision. The only deviation is the approximation of some step sizes. Specifically, we use a channel-shared $\overline{\Delta_{X}}$ rather than channel-wise ${\Delta_{X}}$. From our experiments, this approximation introduces no observable loss in accuracy.

In our actual implementation, the primary source of error in our design originates from the precision error from normalization. In order to fit each multiplication into the $27\times 18$ multiplier of the on-board DSP48E2 unit, we apply scaling in normalization. Derived from Equation 13, our fixed-point normalization has the form

[TABLE]

In Equation 17, two additional terms are introduced: $2^{\nu}$, referred to as the numerator, and $s$, referred to as the prescale factor. The numerator increases the precision of the fractional division by scaling $1/i$ up ($2^{\nu}$x) before the multiplication and scaling down afterward. The scaling-up and scaling-down, achieved from shifter, are lossless, but rounding $2^{\nu}/i$ to an integer introduces quantization error in inference.

The prescale factor $s$ is applied to input $x$ before normalization. This increases $\mu$ by a factor of $s$ and $\sigma^{2}$ by a factor of $s^{2}$, requiring a scale-back afterwards too. Similar to $2^{\nu}$, the subsequent scale-back is also achieved with right shift.

In our implementation, we set $2^{\nu}=64$ and $s=32$. To evaluate the impact of these parameters by sweeping a range of values normalized to our chosen baseline. As shown in Figure 14, the accuracy of our design remain close to that of the previously reported quantized model [8], confirming that our integerization introduce no observable errors. On the other side, when either prescale factor $s$ or numerator $2^{\nu}$ drop below a certain threshold, we observe accuracy degradation. This loss comes from the quantization error from $\lceil 2^{\nu}/i\rfloor$ and $\lceil s\times x_{i}-\mu_{i-1}\rfloor$ respectively.

V-G Accuracy Comparison

To validate the accuracy-power tradeoff of our integerized model, we evaluate the accuracy of DeiT series model [27] and power of the 3-bit integerized design.

To estimate power across hardware using different bitwidth, we adopt the widely used quadratic relationship between multiplier power and bitwidth [31, 32]. Combined with the total number of OPs required per model, the estimated power can be normalized as

[TABLE]

Figure 15 compares the accuracy and normalized power of our model against several prior works, including HG-PIPE [33], Auto-ViT-acc [23], Xiao [34], and I-ViT [7]. We exclude quantization works that rely on dequantized operands, as their computation does not benefit from low-bit arithmetic.

In Figure 15, accuracy and normalized power forms a Pareto frontier from the bottom-left to top-right. The closest point in accuracy to our model is a configuration from Auto-ViT-acc [23], which uses a mix of 3-bit and 4-bit weight along with 4-bit activations. When applying only 3-bit weight in their design, the accuracy drops below ours while still more power consuming. This push in the Pareto frontier demonstrates the effectiveness of our integerization algorithm in achieving superior power efficiency without sacrificing accuracy.

V-H Compare to Same-technology Accelerators

Table III compares our accelerator to other FPGA-based transformer implementations in terms of clock rate, power, gigaoperations per second (GOPs/s), power efficient (GOPs/s/W), bandwidth (GB/s), and operational intensity (OP/byte). Here we use GOPs/s instead of tokens/s to allow cross-model comparison.

Due to the reduced logic used in 3-bit MAC, our design can accommodate more operations within the same hardware resources. Combined with a $400$ MHz operating frequency, we achieve the highest throughput $13,568$ (GOPs/s). This result is even comparable to GPUs using the same technology (Tesla P100: $18,700$ GOPs/s in FP16 and GeForce GTX 1080: $8,873$ GOPs/s in FP32). While comparing low-bit integer operations on FPGAs with FP operations on GPUs is not entirely fair, these results demonstrate the potential of low-bit models.

In terms of power efficiency, our design exceeds that of models using 8-bit or higher precision by more than 2.5x. Even when compared to low-bit accelerator [33], we still have better power efficiency and throughput together. This improvement is driven both by the simplicity of integer operations and our model integerization approach.

Finally, we also optimize bandwidth to improve performance within the roofline model [9]. The combination of low-bit packet and accelerator pipelining enables our design to operate with just $3.13$ (GB/s) of bandwidth, a level that is achievable through PCIe 3.0 x4 protocol. At the same time, our design also delivers an operational intensity of $4342$ (OP/Byte), which is $28$x higher than the existing state-of-the-art works, further explaining the superior performance in the roofline model.

V-I Compare with Other Technology Nodes

We also compare our design against prior works implemented in different technologies. We follow fixed-frequency, constant-field Dennard scaling [42] for a fair comparison. The following relationships are used for normalization

[TABLE]

According to Dennard scaling, when scaling to a more advanced technology by a factor of $\alpha$ ($\alpha>1$), transistor density, gate capacitance $C_{g}$, and supply voltage $V$ scale as $\alpha^{2}$, $\alpha$, and $1/\alpha$ respectively. This estimation results in theoretical improvement of $\alpha^{2}\times$ in throughput and $\alpha\times$ in power efficiency.

Figure 16 presents a comparison of power efficiency and throughput across various FPGA-based transformer accelerators and GPUs from different generation. The GPU specifications are obtained from TechPowerUp database [43]. In throughput, some GPUs have higher throughput than our design. This mainly comes from die size-dependent throughput as die size is not reported in FPGAs. In contrast, our design achieves the highest normalized power efficiency among all evaluated works, validating the effectiveness of our low-bit architecture.

V-J Extended to Full DeiT-S and Other Models

Section V-C discussed the timing performance of the MSA in DeiT-S. In this discussion, we want to provide an estimation to the entire model to show the potential of our low-bit integer inference architecture.

To make a conservative estimation, we assume the MLP operation is implemented in another accelerator. Thus, the MHA and MLP results are transformed back and forth to MLP and MHA accelerators with the costs of four transmission.

Table LABEL:tab:deit-full lists the latency estimation for the full DeiT-S, as well as two of its variant DeiT-T and DeiT-B.

V-K Higher-throughput DSP-free Design

One of the primary computational bottleneck in our design is the $400$MHz clock, which is limited by the timing constraints of the DSP units. To address this limitation, we also explore an alternative DSP-free design to achieve higher clock frequencies.

While removing DSPs allows for faster clocking, it introduces a tradeoff for increased latency due to a deeper pipeline using more cycles. Figure 17 (A) shows the timing diagram for the DSP-free aggregation. As the aggregation unit takes additional cycles, it requires an extra delay cycle to match the timing between the post-MAC unit and the aggregation stage.

Figure 17 (B)(C) illustrates the DSP-free statistics and NormQ. The multiplier is divided into multiple cycles, and the rest of them remains unchanged. Figure 17 (D) visually demonstrates the tradeoff for divided multipliers. Although the total computation time in the DSP-free version $T_{DSPfree}$ is longer than in the original DSP-based version $T_{DSP}$, the resulting clock period $T_{period}$ is shorter than $T_{DSP}$. This enables a faster clock and thus higher throughput overall.

Table VI compares the performance between the DSP-free and DSP-based design. The DSP-free design achieves a higher clock frequency and increased power consumption. To isolate the impact of clock frequency, we also evaluate the DSP-free design under the same $400$ MHz clock. Across both frequency settings, the DSP-free designs exhibits similar power efficiency and GOP per cycle. The version with a $500$ MHz clock achieves proportionally higher power and throughput (GOPs/s) with the faster clock.

At the same frequency, the DSP-free design consumes more power. This is because of the lower energy efficiency of LUT-based arithmetic compared to DSP units. In terms of latency, the multipliers in DSP-free design requires between $2-4$ cycles depending on operand size. This introduces additional $1\times 64+4\times 1+1\times 3=71$ cycles to complete a single SA.

Importantly, the above additional latency does not scale with the number of heads $H$. In the context of the full MSA pipeline, the overhead cost is only $71/11425=0.6\%$, which is small and negligible.

Another drawback of the DSP-free design is its reduced power efficiency. Replacing DSP with look-up table and pipeline register takes extra 56.7% power cost. In server-based application, this increased power is equivalent to increased cost from the same inference, limiting the practicality of adopting DSP-free architectures despite their frequency advantages.

VI Conclusions

In this paper, we presented a low-bit, systolic array-based architecture to enhance both throughput and power efficiency for transformer model inference. The proposed architecture employs systolic-compatible units to construct a deep and fine-grained pipeline. The operational intensity is optimized by low communication-overhead transmission point and large compute density from simple low-bit arithmetic. We validate our approach by implementing the system on an FPGA (Alveo U250). The system achieves 77.81% top-1 accuracy on ImageNet, delivers a throughput of 13,568 GOPs/s at 61.83 W. The power efficiency 219.4 GOPs/s/W outperforms state-of-the-art solutions and demonstrates the effectiveness of our low-bit, systolic-based design for efficient transformer inference.