Support Vector Machines Classification on Bendable RISC-V

TL;DR

This paper introduces a novel SVM accelerator architecture integrated with a flexible RISC-V core, achieving significant improvements in inference speed and energy efficiency for flexible electronics applications.

Contribution

It presents a new open-source framework and a custom ML accelerator architecture supporting scalable precision for SVMs on bendable RISC-V processors.

Findings

21x faster inference execution time

21x energy efficiency improvement

Supports multiple precision levels (4, 8, 16-bit)

Abstract

Flexible Electronics (FE) technology offers uniquecharacteristics in electronic manufacturing, providing ultra-low-cost, lightweight, and environmentally-friendly alternatives totraditional rigid electronics. These characteristics enable a rangeof applications that were previously constrained by the costand rigidity of conventional silicon technology. Machine learning (ML) is essential for enabling autonomous, real-time intelligenceon devices with smart sensing capabilities in everyday objects. However, the large feature sizes and high power consumption ofthe devices oppose a challenge in the realization of flexible ML applications. To address the above, we propose an open-source framework for developing ML co-processors for the Bendable RISC-V core. In addition, we present a custom ML accelerator architecture for Support Vector Machine (SVM), supporting both one-vs-one (OvO) and one-vs-rest (OvR) algorithms. Our ML accelerator adopts a generic, precision-scalable design, supporting 4-, 8-, and 16-bit weight representations. Experimental results demonstrate a 21x improvement in both inference execution time and energy efficiency, on average, highlighting its potential for low-power, flexible intelligence on the edge.