Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges

TL;DR

This paper explores how 3D die stacking and 2.5D interposers can be utilized to enhance hardware security, addressing challenges like side channel attacks, hardware trojans, and IP piracy through novel design approaches.

Contribution

It introduces new security-oriented designs leveraging 3D technologies, including shielding architectures, split fabrication, circuit camouflage, and security processing-in-memory.

Findings

3D architectures can effectively shield against side-channel attacks.

Split fabrication with active interposers enhances security.

3D IC-based PIM offers new security features.

Abstract

3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing countermeasures against security threats and further provide new security features.