SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study
Yang Xiang, Fernando Garc\'ia-Redondo, Arvind Sharma, Van Dai Nguyen, Andrea Fantini, Philippe Matagne, Siddharth Rao, Subhali Subhechha, Lynn Verschueren, Mohammed Aftab Baig, Marie Garcia Bardon, Geert Hellings

TL;DR
This paper evaluates the potential of using BEOL read selectors to improve the scaling of SOT-MRAM bitcells at 7 nm technology, addressing area, power, and performance tradeoffs through extensive DTCO analysis.
Contribution
It introduces BEOL read selectors as a solution to the scaling challenges of SOT-MRAM bitcells, demonstrating area reduction and performance considerations at 7 nm.
Findings
BEOL RSs enable 10-40% bitcell area reduction.
BEOL RS-based bitcells can meet writability requirements with proper magnetic layer engineering.
Tradeoffs include increased latency and energy costs with certain selector types.
Abstract
This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate the bitcell footprint for different cell configurations at a representative 7 nm technology and to assess their implications on read and write power-performance. We crucially identify the MTJ routing struggle in conventional two-transistor one-resistor (2T1R) SOT-MRAMs as the primary bitcell area scaling challenge and propose to use BEOL read selectors (BEOL RSs) that enable (10 -- 40) % bitcell area reduction and eventually match sub-N3 SRAM. On writability, we affirm that BEOL RS-based bitcells could meet the required SOT switching current, provided the magnetic free layer properties be engineered in line with LLC-specific, (0.1 -- 100) s retention targets. This is…
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