TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates

TL;DR

TLGLock introduces a scalable, energy-efficient logic locking method using threshold logic gates and charge recycling, significantly improving security and reducing overhead compared to traditional techniques.

Contribution

It presents a novel lock design leveraging threshold logic gates and charge recycling, offering enhanced security, lower overhead, and a complete synthesis-to-locking flow.

Findings

Achieves up to 30% area reduction.

Provides up to 50% delay improvement.

Offers up to 3x higher SAT attack resistance.

Abstract

Logic locking remains one of the most promising defenses against hardware piracy, yet current approaches often face challenges in scalability and design overhead. In this paper, we present TLGLock, a new design paradigm that leverages the structural expressiveness of Threshold Logic Gates (TLGs) and the energy efficiency of charge recycling to enforce key-dependent functionality at the gate level. By embedding the key into the gate's weighted logic and utilizing dynamic charge sharing, TLGLock provides a stateless and compact alternative to conventional locking techniques. We implement a complete synthesis-to-locking flow and evaluate it using ISCAS, ITC, and MCNC benchmarks. Results show that TLGLock achieves up to 30% area, 50% delay, and 20% power savings compared to latch-based locking schemes. In comparison with XOR and SFLL-HD methods, TLGLock offers up to 3x higher SAT attack resistance with significantly lower overhead. Furthermore, randomized key-weight experiments demonstrate that TLGLock can reach up to 100% output corruption under incorrect keys, enabling tunable security at minimal cost. These results position TLGLock as a scalable and resilient solution for secure hardware design.