Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
Zhihao Xu, Shikai Guo, Guilin Zhao, Siwen Wang, Qian Ma, Hui Li, Furui Zhan

TL;DR
This paper introduces LSC-Fuzz, a Bayesian optimization-guided mutation testing approach for FPGA logic synthesis compilers, significantly improving bug detection in safety-critical FPGA applications.
Contribution
It presents a novel guided mutation strategy using Bayesian optimization for more effective FPGA compiler testing, outperforming previous simple mutation methods.
Findings
Discovered 16 bugs in FPGA logic synthesis compilers
12 bugs confirmed by official support
Enhanced bug detection with Bayesian-guided test generation
Abstract
Field Programmable Gate Arrays (FPGAs) play a crucial role in Electronic Design Automation (EDA) applications, which have been widely used in safety-critical environments, including aerospace, chip manufacturing, and medical devices. A critical step in FPGA development is logic synthesis, which enables developers to translate their software designs into hardware net lists, which facilitates the physical implementation of the chip, detailed timing and power analysis, gate-level simulation, test vector generation, and optimization and consistency checking. However, bugs or incorrect implementations in FPGA logic synthesis compilers may lead to unexpected behaviors in target wapplications, posing security risks. Therefore, it is crucial to eliminate such bugs in FPGA logic synthesis compilers. The effectiveness of existing works is still limited by its simple, blind mutation strategy. To…
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Taxonomy
TopicsFormal Methods in Verification · Software Testing and Debugging Techniques · Radiation Effects in Electronics
