X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications

TL;DR

X-HEEP is an open-source, highly configurable RISC-V platform optimized for TinyAI edge applications, supporting diverse accelerators and development flows, with demonstrated low power and significant performance gains.

Contribution

We introduce X-HEEP, a novel extendible RISC-V platform with a unique XAIF interface, enabling flexible integration of accelerators and supporting multiple design flows.

Findings

Achieves 0.15 mm2 footprint and 29 uW leakage power in 65 nm CMOS.

Demonstrates up to 7.3x performance speedup with near-memory accelerators.

Provides 3.6x energy efficiency improvement over CPU-only systems.

Abstract

In this work, we present X-HEEP, an open-source, configurable, and extendible RISC-V platform for ultra-low-power edge applications (TinyAI). X-HEEP features the eXtendible Accelerator InterFace (XAIF), which enables seamless integration of accelerators with varying requirements along with an extensive internal configuration of cores, memory, bus, and peripherals. Moreover, it supports various development flows, including FPGA prototyping, ASIC implementation, and mixed SystemC-RTL modeling, enabling efficient exploration and optimization. Implemented in TSMC's 65 nm CMOS technology (300 MHz, 0.8 V), X-HEEP achieves a minimal footprint of only 0.15 mm2 and consumes just 29 uW of leakage power. As a demonstrator of the configurability and low overhead of X-HEEP as a host platform, we present a study integrating it with near-memory accelerators targeting early-exit dynamic network applications, achieving up to 7.3 x performance speedup and 3.6 x energy improvement on the resulting heterogeneous system compared to CPU-only execution.