TSPC-PFD: TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector

TL;DR

This paper introduces a novel TSPC-based CMOS phase frequency detector that eliminates blind zones and minimizes dead zones, achieving high resolution and low power consumption suitable for high-speed PLL and DLL systems.

Contribution

It presents a new TSPC-based PFD design that completely removes blind zones and significantly reduces dead zones, improving phase detection accuracy in high-speed applications.

Findings

Eliminates blind zone in PFD design

Achieves dead zone of only 40 ps

Consumes 4.41 μW power at 3 GHz

Abstract

Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD designs often suffer from significant dead zones and blind zones, which degrade phase detection accuracy and increase jitter in high-speed applications. This paper addresses PFD design challenges and presents a novel low-power True Single-Phase Clock (TSPC)-based PFD. The proposed design eliminates the blind zone entirely while achieving a minimal dead zone of 40 ps. The proposed PFD, implemented using TSMC 28 nm technology, demonstrates a low-power consumption of 4.41 uW at 3 GHz input frequency with a layout area of $10.42\mu m^2$.