ARSP: Automated Repair of Verilog Designs via Semantic Partitioning

TL;DR

ARSP introduces a semantic partitioning approach to improve automated Verilog bug fixing with LLMs, significantly outperforming existing tools and models by reducing context dilution.

Contribution

The paper presents a novel two-stage semantic partitioning system that enhances LLM-based Verilog debugging by focusing on semantically tight fragments, improving accuracy and scalability.

Findings

ARSP achieves 77.92% pass@1, outperforming commercial LLMs.

Semantic partitioning improves debugging success by over 10%.

Fragment-level scope reduction enhances LLM effectiveness.

Abstract

Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this effort, existing LLM-based automated debugging methods underperform on industrial-scale modules. A major reason for this is bug signal dilution in long contexts, where a few bug-relevant tokens are overwhelmed by hundreds of unrelated lines, diffusing the model's attention. To address this issue, we introduce ARSP, a two-stage system that mitigates dilution via semantics-guided fragmentation. A Partition LLM splits a module into semantically tight fragments; a Repair LLM patches each fragment; edits are merged without altering unrelated logic. A synthetic data framework generates fragment-level training pairs spanning bug types, design styles, and scales to supervise both models. Experiments show that ARSP achieves 77.92% pass@1 and 83.88% pass@5, outperforming mainstream commercial LLMs including Claude-3.7 and SOTA automated Verilog debugging tools Strider and MEIC. Also, semantic partitioning improves pass@1 by 11.6% and pass@5 by 10.2% over whole-module debugging, validating the effectiveness of fragment-level scope reduction in LLM-based Verilog debugging.