Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference

TL;DR

This paper introduces a specialized SoC combining RISC-V and NVDLA for efficient deep learning inference at the edge, utilizing a bare-metal software flow to optimize speed and storage.

Contribution

It presents a novel tightly coupled RISC-V and NVDLA architecture with a bare-metal toolflow, improving inference speed and efficiency for edge deep learning applications.

Findings

Inference times: 4.8 ms for LeNet-5, 16.2 ms for ResNet-18, 1.1 s for ResNet-50.

Achieved on AMD ZCU102 FPGA with 100 MHz system clock.

Bare-metal approach reduces OS overheads, enhancing performance.

Abstract

This paper presents a novel System-on-Chip (SoC) architecture for accelerating complex deep learning models for edge computing applications through a combination of hardware and software optimisations. The hardware architecture tightly couples the open-source NVIDIA Deep Learning Accelerator (NVDLA) to a 32-bit, 4-stage pipelined RISC-V core from Codasip called uRISC_V. To offload the model acceleration in software, our toolflow generates bare-metal application code (in assembly), overcoming complex OS overheads of previous works that have explored similar architectures. This tightly coupled architecture and bare-metal flow leads to improvements in execution speed and storage efficiency, making it suitable for edge computing solutions. We evaluate the architecture on AMD's ZCU102 FPGA board using NVDLA-small configuration and test the flow using LeNet-5, ResNet-18 and ResNet-50 models. Our results show that these models can perform inference in 4.8 ms, 16.2 ms and 1.1 s respectively, at a system clock frequency of 100 MHz.