A 16.28 ppm/$^\circ$C Temperature Coefficient, 0.5V Low-Voltage CMOS Voltage Reference with Curvature Compensation
Harshith Reddy, Pankaj Arora

TL;DR
This paper introduces a low-voltage CMOS voltage reference with an exceptionally low temperature coefficient of 16.28 ppm/°C, achieved through curvature compensation, operating at 0.5 V in 90 nm technology.
Contribution
It presents a fully-integrated CMOS voltage reference with curvature compensation, achieving low temperature drift at ultra-low voltage in 90 nm process.
Findings
Temperature coefficient of 16.28 ppm/°C achieved
Stable 205 mV reference voltage over wide temperature range
Power consumption of only 0.67 μW
Abstract
This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion characteristics, backed by an all-region MOSFET model. The proposed design achieves a very low operating supply voltage of 0.5 V and a remarkably low temperature coefficient of 16.28 ppm/C through the mutual compensation of CTAT, PTAT, and curvature-correction currents, over a wide range from -40 C to 130 C. A stable reference voltage of 205 mV is generated with a line sensitivity of 1.65 %/V and a power supply rejection ratio (PSRR) of -50 dB at 10 kHz. The circuit achieves all these parameters while maintaining a good power efficiency, consuming only 0.67 W.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAnalog and Mixed-Signal Circuit Design · Low-power high-performance VLSI design · Advancements in PLL and VCO Technologies
