A Novel Mutation Based Method for Detecting FPGA Logic Synthesis Tool Bugs
Yi Zhang, He Jiang, Xiaochen Li, Shikai Guo, Peiyu Zou, Zun Wang

TL;DR
This paper introduces VERMEI, a new semantic testing method for FPGA logic synthesis tools that generates complex, equivalent program variants to effectively identify bugs and improve tool reliability.
Contribution
The paper presents VERMEI, a novel mutation-based testing approach that enhances bug detection in FPGA synthesis tools by generating complex, equivalent variants using Bayesian sampling.
Findings
VERMEI outperforms existing methods in bug detection.
Reported 15 bugs to vendors, with 9 confirmed as new.
Successfully identified complex bugs in FPGA synthesis tools.
Abstract
FPGA (Field-Programmable Gate Array) logic synthesis tools are key components in the EDA (Electronic Design Automation) toolchain. They convert hardware designs written in description languages such as Verilog into gate-level representations for FPGAs. However, defects in these tools may lead to unexpected behaviors and pose security risks. Therefore, it is crucial to harden these tools through testing. Although several methods have been proposed to automatically test FPGA logic synthesis tools, the challenge remains of insufficient semantic and logical complexity in test programs. In this paper, we propose VERMEI, a new method for testing FPGA logic synthesis tools. VERMEI consists of three modules: preprocessing, equivalent mutation, and bug identification. The preprocessing module identifies zombie logic (inactive code with no impact on the circuit output) in seed programs through…
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Taxonomy
TopicsSoftware Testing and Debugging Techniques · Formal Methods in Verification · Radiation Effects in Electronics
