Fermion-to-Fermion Low-Density Parity-Check Codes

TL;DR

This paper introduces a fault-tolerant quantum computing protocol that directly encodes fermionic systems using fermion-to-fermion LDPC codes, reducing resource demands and improving error suppression.

Contribution

It presents a novel fermionic LDPC code-based protocol with logical Majorana operators, enabling efficient fermionic quantum computation and state transfer methods.

Findings

Encoding rate comparable to qubit codes

Logical failure rate lower than physical error rate

Effective error suppression demonstrated in simulations

Abstract

Simulating fermionic systems on qubit-based quantum computers often demands significant computational resources due to the requirement to map fermions to qubits. Thus, designing a fault-tolerant quantum computer that operates directly with fermions offers an effective solution to this challenge. Here, we introduce a protocol for fault-tolerant fermionic quantum computation utilizing fermion-to-fermion low-density parity-check (LDPC) codes. Our method employs a fermionic LDPC memory, which transfers its state to fermionic color code processors, where logical operations are subsequently performed. We propose using odd-weight logical Majorana operators to form the code space, serving as memory for the fermionic LDPC code, and provide an algorithm to identify these logical operators. We present examples showing that the encoding rate of fermionic codes often matches that of qubit codes, while the logical failure rate can be significantly lower than the physical error rate. Furthermore, we propose two methods for performing fermionic lattice surgery to facilitate state transfer. Finally, we simulate the dynamics of a fermionic system using our protocol, illustrating effective error suppression.