ListenToJESD204B: A Lightweight Open-Source JESD204B IP Core for FPGA-Based Ultrasound Acquisition systems

TL;DR

This paper introduces ListenToJESD204B, an open-source, resource-efficient FPGA IP core for high-speed ultrasound data acquisition, offering a cost-effective alternative to proprietary solutions with verified high-speed data streaming capabilities.

Contribution

It presents a lightweight, open-source JESD204B receiver IP core optimized for FPGA implementation, supporting high data rates with reduced resource usage and verified protocol compliance.

Findings

Supports four GTH/GTY lanes at 12.8 Gb/s

Reduces resource usage by 79% compared to commercial IP

Successfully streams 80 MSPS, 16-bit samples over two links for 30 minutes without errors

Abstract

The demand for hundreds of tightly synchronized channels operating at tens of MSPS in ultrasound systems exceeds conventional low-voltage differential signaling links' bandwidth, pin count, and latency. Although the JESD204B serial interface mitigates these limitations, commercial FPGA IP cores are proprietary, costly, and resource-intensive. We present ListenToJESD204B, an open-source receiver IP core released under a permissive Solderpad 0.51 license for AMD Xilinx Zynq UltraScale+ devices. Written in synthesizable SystemVerilog, the core supports four GTH/GTY lanes at 12.8 Gb/s and provides cycle-accurate AXI-Stream data alongside deterministic Subclass~1 latency. It occupies only 107 configurable logic blocks (approximately 437 LUTs), representing a 79\% reduction compared to comparable commercially available IP. A modular data path featuring per-lane elastic buffers, SYSREF-locked LMFC generation, and optional LFSR descrambling facilitates scaling to high lane counts. We verified protocol compliance through simulation against the Xilinx JESD204C IP in JESD204B mode and on hardware using TI AFE58JD48 ADCs. Block stability was verified by streaming 80 MSPS, 16-bit samples over two 12.8 Gb/s links for 30 minutes with no errors.