ViTAD: Timing Violation-Aware Debugging of RTL Code using Large Language Models
Wenhao Lv, Yingjie Xia, Xiyuan Chen, Li Kuang

TL;DR
ViTAD automates the debugging of timing violations in RTL code by combining graph analysis, large language models, and domain knowledge, significantly improving repair success rates over baseline methods.
Contribution
This paper introduces ViTAD, a novel approach that integrates signal dependency analysis, LLMs, and domain knowledge to automate timing violation debugging in RTL design.
Findings
Achieves a 73.68% success rate in repairing timing violations.
Outperforms baseline LLM-only approach by 19.30%.
Constructed a real-world dataset of 54 violation cases.
Abstract
In modern Very Large Scale Integrated (VLSI) circuit design flow, the Register-Transfer Level (RTL) stage presents a critical opportunity for timing optimization. Addressing timing violations at this early stage is essential, as modern systems demand higher speeds, where even minor timing violations can lead to functional failures or system crashes. However, traditional timing optimization heavily relies on manual expertise, requiring engineers to iteratively analyze timing reports and debug. To automate this process, this paper proposes ViTAD, a method that efficiently analyzes the root causes of timing violations and dynamically generates targeted repair strategies. Specifically, we first parse Verilog code and timing reports to construct a Signal Timing Dependency Graph (STDG). Based on the STDG, we perform violation path analysis and use large language models (LLMs) to infer the…
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