Towards Capacitive In-Memory-computing: A perspective on the future of AI hardware

TL;DR

This paper discusses the potential of capacitive memories for energy-efficient, scalable in-memory computing in AI hardware, highlighting their advantages over memristive memories and exploring device and system-level trade-offs.

Contribution

It provides a comprehensive perspective on capacitive in-memory computing, emphasizing device-level advantages and system trade-offs for future AI hardware development.

Findings

Capacitive memories enable charge-domain computation with near-zero static power.

They are immune to sneak-path currents and compatible with 3D integration.

Material engineering can modulate synaptic behavior and storage capabilities.

Abstract

The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive memories have been extensively explored for synaptic implementation in CIM architectures, their inherent limitations, including static power dissipation, sneak-path currents, and interconnect voltage drops, pose significant challenges for large-scale deployment, particularly at advanced technology nodes. In contrast, capacitive memories offer a compelling alternative by enabling charge-domain computation with virtually zero static power loss, intrinsic immunity to sneak paths, and simplified selector-less crossbar operation, while offering superior compatibility with 3D Back-end-of-Line (BEOL) integration. This perspective highlights the architectural and device-level advantages of emerging non-volatile capacitive synapses. We examine how material engineering and interface control can modulate synaptic behavior, capacitive memory window and multilevel analog storage potential. Furthermore, we explore critical system-level trade-offs involving device-to-device variation, charge transfer noise, dynamic range, and effective analog resolution.