FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design
Mahmoud Nazzal, Khoa Nguyen, Deepak Vungarala, Ramtin Zand, Shaahin Angizi, Hai Phan, Abdallah Khreishah

TL;DR
FedChip introduces a federated learning approach for collaborative fine-tuning of large language models in AI hardware design, enhancing design quality while preserving proprietary data privacy.
Contribution
The paper presents FedChip, a novel federated fine-tuning method for LLMs in chip design, and releases a new dataset and evaluation metric for multi-objective design generation.
Findings
FedChip improves design quality by over 77% compared to high-end LLMs.
The approach maintains data privacy across multiple design parties.
The new Chip@k metric effectively evaluates multi-criteria design quality.
Abstract
AI hardware design is advancing rapidly, driven by the promise of design automation to make chip development faster, more efficient, and more accessible to a wide range of users. Amongst automation tools, Large Language Models (LLMs) offer a promising solution by automating and streamlining parts of the design process. However, their potential is hindered by data privacy concerns and the lack of domain-specific training. To address this, we introduce FedChip, a Federated fine-tuning approach that enables multiple Chip design parties to collaboratively enhance a shared LLM dedicated for automated hardware design generation while protecting proprietary data. FedChip enables parties to train the model on proprietary local data and improve the shared LLM's performance. To exemplify FedChip's deployment, we create and release APTPU-Gen, a dataset of 30k design variations spanning various…
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