Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner

TL;DR

Piano is a novel floorplanning framework that simultaneously optimizes module placement and pin assignment under multiple constraints, significantly improving layout quality in VLSI design.

Contribution

It introduces a graph-based method for integrated pin assignment and placement optimization, addressing modern constraints often overlooked in traditional floorplanning.

Findings

Achieves 6.81% reduction in HPWL

Reduces feedthrough wirelength by 13.39%

Decreases unplaced pins by 21.21%

Abstract

Floorplanning is a critical step in VLSI physical design, increasingly complicated by modern constraints such as fixed-outline requirements, whitespace removal, and the presence of pre-placed modules. In addition, the assignment of pins on module boundaries significantly impacts the performance of subsequent stages, including detailed placement and routing. However, traditional floorplanners often overlook pin assignment with modern constraints during the floorplanning stage. In this work, we introduce Piano, a floorplanning framework that simultaneously optimizes module placement and pin assignment under multiple constraints. Specifically, we construct a graph based on the geometric relationships among modules and their netlist connections, then iteratively search for shortest paths to determine pin assignments. This graph-based method also enables accurate evaluation of feedthrough and unplaced pins, thereby guiding overall layout quality. To further improve the design, we adopt a whitespace removal strategy and employ three local optimizers to enhance layout metrics under multi-constraint scenarios. Experimental results on widely used benchmark circuits demonstrate that Piano achieves an average 6.81% reduction in HPWL, a 13.39% decrease in feedthrough wirelength, a 16.36% reduction in the number of feedthrough modules, and a 21.21% drop in unplaced pins, while maintaining zero whitespace.