Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits

TL;DR

This paper introduces a thermal-aware design method for 3-D ICs that optimizes TSV via farm placement to reduce lateral heat blockages and improve thermal management in densely packed structures.

Contribution

It presents a novel via farm placement technique that considers lateral thermal effects, addressing a key challenge in thermally efficient 3-D IC design.

Findings

Reduces local hotspots in 3-D ICs with dense TSV farms.

Improves thermal distribution by optimizing via placement.

Enhances overall thermal efficiency of 3-D integrated circuits.

Abstract

3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in {\mu}m range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures.