Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures

TL;DR

This paper introduces three novel reduction methods for RC long-chain structures in transistor-level circuit simulations, significantly improving simulation speed while maintaining high accuracy, thus enhancing the efficiency of circuit validation processes.

Contribution

The paper presents new reduction techniques specifically designed for RC long-chain structures, reducing simulation complexity and time without sacrificing accuracy.

Findings

Average performance improvement of 8.8% in simulation speed

Up to 22% speedup achieved on benchmark circuits

Only 0.7% relative error maintained in results

Abstract

Transistor-level simulation plays a vital role in validating the physical correctness of integrated circuits. However, such simulations are computationally expensive. This paper proposes three novel reduction methods specifically tailored to RC long-chain structures with different scales of time constant. Such structures account for an average of 6.34\% (up to 12\%) of the total nodes in the benchmark circuits. Experimental results demonstrate that our methods yields an average performance improvement of 8.8\% (up to 22\%) on simulating benchmark circuits which include a variety of functional modules such as ALUs, adders, multipliers, SEC/DED checkers, and interrupt controllers, with only 0.7\% relative error.