Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration

TL;DR

This paper introduces a novel cube packing engine for fine grain 3D integration in microarchitecture design, enabling optimized physical and architectural exploration for improved performance, power, and thermal management.

Contribution

It presents a new cube packing approach that allows multi-layer logical blocks, enhancing 3D IC design exploration with integrated physical and architectural optimization tools.

Findings

36% performance improvement over 2D designs

14% performance gain over single-layer 3D designs

Up to 30% power reduction with multi-layer blocks

Abstract

Most previous 3D IC research focused on stacking traditional 2D silicon layers, so the interconnect reduction is limited to inter-block delays. In this paper, we propose techniques that enable efficient exploration of the 3D design space where each logical block can span more than one silicon layers. Although further power and performance improvement is achievable through fine grain 3D integration, the necessary modeling and tool infrastructure has been mostly missing. We develop a cube packing engine which can simultaneously optimize physical and architectural design for effective utilization of 3D in terms of performance, area and temperature. Our experimental results using a design driver show 36% performance improvement (in BIPS) over 2D and 14% over 3D with single layer blocks. Additionally multi-layer blocks can provide up to 30% reduction in power dissipation compared to the single-layer alternatives. Peak temperature of the design is kept within limits as a result of thermal-aware floorplanning and thermal via insertion techniques.