EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code

TL;DR

EvoVerilog is a framework that combines language models with evolutionary algorithms to automatically generate and optimize Verilog hardware designs, achieving state-of-the-art results without human intervention.

Contribution

It introduces a multiobjective, population-based search method that enhances diversity and performance in automated Verilog code generation using LLMs.

Findings

Achieves pass@10 scores of 89.1 on VerilogEval-Machine

Generates diverse functional Verilog designs

Optimizes resource utilization effectively

Abstract

Large Language Models (LLMs) have demonstrated great potential in automating the generation of Verilog hardware description language code for hardware design. This automation is critical to reducing human effort in the complex and error-prone process of hardware design. However, existing approaches predominantly rely on human intervention and fine-tuning using curated datasets, limiting their scalability in automated design workflows. Although recent iterative search techniques have emerged, they often fail to explore diverse design solutions and may underperform simpler approaches such as repeated prompting. To address these limitations, we introduce EvoVerilog, a novel framework that combines the reasoning capabilities of LLMs with evolutionary algorithms to automatically generate and refine Verilog code. EvoVerilog utilizes a multiobjective, population-based search strategy to explore a wide range of design possibilities without requiring human intervention. Extensive experiments demonstrate that EvoVerilog achieves state-of-the-art performance, with pass@10 scores of 89.1 and 80.2 on the VerilogEval-Machine and VerilogEval-Human benchmarks, respectively. Furthermore, the framework showcases its ability to explore diverse designs by simultaneously generating a variety of functional Verilog code while optimizing resource utilization.