SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip
Ziteng Hu, Yingjie Xia, Xiyuan Chen, Li Kuang

TL;DR
SecFSM enhances the security of Verilog code for FSMs in SoC by guiding LLMs with a security knowledge graph, significantly reducing vulnerabilities in generated code.
Contribution
This paper introduces SecFSM, a novel approach that integrates a security knowledge graph with LLMs to generate more secure Verilog FSM code, addressing security issues in automated code generation.
Findings
SecFSM achieves a 21/25 pass rate on security test cases.
It outperforms state-of-the-art baselines in generating secure Verilog code.
The method effectively reduces vulnerabilities in LLM-generated FSM code.
Abstract
Finite State Machines (FSMs) play a critical role in implementing control logic for Systems-on-Chip (SoC). Traditionally, FSMs are implemented by hardware engineers through Verilog coding, which is often tedious and time-consuming. Recently, with the remarkable progress of Large Language Models (LLMs) in code generation, LLMs have been increasingly explored for automating Verilog code generation. However, LLM-generated Verilog code often suffers from security vulnerabilities, which is particularly concerning for security-sensitive FSM implementations. To address this issue, we propose SecFSM, a novel method that leverages a security-oriented knowledge graph to guide LLMs in generating more secure Verilog code. Specifically, we first construct a FSM Security Knowledge Graph (FSKG) as an external aid to LLMs. Subsequently, we analyze users' requirements to identify vulnerabilities and get…
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