Theoretical Investigation of Performance-Improved Ferroelectric Tunnel Junction Based on Trap-Assisted Tunneling

TL;DR

This paper presents a theoretical model of a ferroelectric tunnel junction utilizing trap-assisted tunneling to significantly enhance current density and on-off ratios, advancing in-memory computing technology.

Contribution

It introduces a comprehensive TAT-based FTJ model that overcomes limitations of conventional FTJs, demonstrating potential for high-performance in-memory computing applications.

Findings

Achieves ultra-high current density in simulations.

Demonstrates a remarkable on-off current ratio.

Highlights the potential for nanoscale IMC applications.

Abstract

CMOS-compatible HfO2-based ferroelectric tunnel junction (FTJ) has attracted significant attention as a promising candidate for in-memory computing (IMC) due to its extremely low power consumption. However, conventional FTJs face inherent challenges that hinder their practical applications. Insufficient current density and limited on-off current ratios in FTJs are primarily constrained by their dependence on direct and Fowler-Nordheim tunneling mechanisms. Building on previous experimental results, this paper proposes a trap-assisted tunneling (TAT)-based FTJ that leverages the TAT mechanism to overcome these limitations. A comprehensive FTJ model integrating ferroelectric switching, direct, Fowler-Nordheim tunneling, and TAT mechanisms is developed, enabling detailed analyses of the trap conditions and their impact on performance. Through systematic optimization of trap parameters and device structure, the simulated TAT-based FTJ achieves ultra-high current density and a remarkable on-off current ratio, meeting the nanoscale IMC requirements. The results highlight the potential of TAT-based FTJs as high-performance memory solutions for IMC applications.