MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem

TL;DR

MemorySim is an RTL-level memory simulator compatible with Chisel/Verilog, providing accurate timing and correctness for AI hardware design, enabling precise performance and power analysis.

Contribution

MemorySim introduces an RTL-level memory simulation model that ensures both timing accuracy and functional correctness within the Chisel ecosystem.

Findings

Provides precise timing and correctness in memory simulation.

Seamlessly integrates with Chisel/Verilog and FireSim.

Enables accurate performance and power estimation for AI hardware.

Abstract

The rapid growth of AI applications has driven increased demand for specialized AI hardware, highlighting critical opportunities within the memory subsystem, which often serves as a performance bottleneck in high-demand workloads such as large language models (LLMs). Existing high-level memory simulators, such as DRAMSim2 and DRAMSim3, offer timing simulations but frequently compromise on correctness or integration at the register-transfer level (RTL). We present MemorySim, an RTL-level memory simulator designed to deliver both accurate timing and functional correctness. MemorySim integrates seamlessly with existing Chisel and Verilog simulations and is fully compatible with the Chisel/Chipyard ecosystem. This enables users to obtain precise performance and power estimates, supporting downstream evaluation through simulation platforms such as FireSim.