Soft Error Probability Estimation of Nano-scale Combinational Circuits

TL;DR

This paper presents a comprehensive framework for estimating soft error probability in nano-scale circuits by integrating process variation and aging effects, offering high accuracy with reduced computational effort.

Contribution

It introduces a novel holistic approach combining electrical masking, process variation, and aging effects for efficient SEP estimation in nano-scale circuits.

Findings

Achieves high accuracy in SEP estimation.

Reduces computational overhead by approximately 2.5%.

Enables more reliable nano-scale circuit design.

Abstract

As technology scales, nano-scale digital circuits face heightened susceptibility to single event upsets (SEUs) and transients (SETs) due to shrinking feature sizes and reduced operating voltages. While logical, electrical, and timing masking effects influence soft error probability (SEP), the combined impact of process variation (PV) and aging-induced degradation further complicates SEP estimation. Existing approaches often address PV or aging in isolation, or rely on computationally intensive methods like Monte Carlo simulations, limiting their practicality for large-scale circuit optimization. This paper introduces a novel framework for SEP analysis that holistically integrates PV and aging effects. We propose an enhanced electrical masking model and a statistical methodology to quantify soft error probability under process and aging variations. Experimental results demonstrate that the proposed approach achieves high accuracy while reducing computational overhead by approximately 2.5% compared to Monte Carlo-based methods. This work advances the design of reliable nano-scale circuits by enabling efficient, accurate SEP estimation in the presence of manufacturing variability and long-term transistor degradation.