Design of a Timer Queue Supporting Dynamic Update Operations

TL;DR

This paper introduces a novel hardware timer queue supporting dynamic updates, significantly improving efficiency and accuracy for large-scale network timers through a hybrid systolic array architecture.

Contribution

It presents the first hardware priority queue capable of in-queue priority updates, combining systolic arrays and shift registers for high-speed, resource-efficient timer management.

Findings

Operates at over 400 MHz on FPGAs

Reduces resource consumption by 2.2-2.8x

Supports five operations including update and delete

Abstract

Large-scale timers are ubiquitous in network processing, including flow table entry expiration control in software defined network (SDN) switches, MAC address aging in Ethernet bridges, and retransmission timeout management in TCP/IP protocols. Conventional implementations suffer from critical limitations: low timing accuracy due to large-scale timer traversal and high computational overhead for new timer insertion. This paper presents a hybrid-architecture hardware priority queue based on systolic arrays and shift registers for efficient timer queue management. The design uniquely supports five operations: enqueue, dequeue, delete, update, and peek.To the best of our knowledge, it is the first hardware priority queue enabling in-queue priority updates. By leveraging centralized Boolean logic encoding within systolic blocks, the design efficiently generates set/shift control signals while the novel push-first operation ensures FIFO ordering for same-priority timers without additional metadata. Experimental results demonstrate that the design operates at over 400 MHz on FPGAs, achieving a 2.2-2.8x reduction in resource consumption compared to state-of-the-art implementations.