Design and Simulation of 6T SRAM Array

TL;DR

This paper presents the design, simulation, and analysis of a 6T SRAM array, including key components and performance metrics, using both theoretical calculations and LTSpice simulations.

Contribution

It provides a comprehensive design and simulation framework for 6T SRAM arrays, analyzing parasitic effects and performance compared to flip-flops.

Findings

CMOS 6T SRAM cells achieve stability, speed, and power efficiency under certain constraints.

Simulation results match theoretical calculations, validating the design approach.

Parasitic capacitances significantly impact waveform behavior and performance.

Abstract

Conventional 6T SRAM is used in microprocessors in the cache memory design. The basic 6T SRAM cell and a 6 bit memory array layout are designed in LEdit. The design and analysis of key SRAM components, sense amplifiers, decoders, write drivers and precharge circuits are also provided. The pulse voltage waveforms generated for read and write operations as well as Q and Qbar nodes are simulated in LTSpice. Parasitic capacitances are extracted and their impact on the waveforms analyzed. Static noise margin, propagation delays, and power dissipation are calculated. Comparison of SRAM read and write operational performance using CMOS transistors is made with edge-triggered D flip flops. If certain size area and ratio constraints are satisfied, the 6T cell with CMOS transistors will possess stability, speed, and power efficiency. Both theoretical and simulated results are given.