A 28nm Multiply-Accumulate ASIC Architecture for On-Chip Data Compression in MHz Frame Rate X-ray and Electron Pixel Detectors

TL;DR

This paper presents a 28nm ASIC architecture for on-chip data compression in high-speed X-ray and electron detectors, enabling efficient data handling at MHz frame rates through a fixed-length lossy compression scheme.

Contribution

It introduces a novel ASIC implementation of a streaming fixed-length lossy compression scheme using vector matrix product logic tailored for pixel detectors.

Findings

ASIC fits within available area for 192x168 pixel detector

Compression ratios from 100 to 250 analyzed

Feasibility of on-chip fixed-length compression demonstrated

Abstract

Modern X-ray detector systems urgently require compact, efficient, and fast data compression schemes to handle the transmission of big data from pixel arrays, enabling frame rates in the MHz regime. In this work, a data compression ASIC that implements a streaming fixed-length lossy compression scheme is introduced and analyzed, proving the feasibility and benefits of on-chip compression. The compression scheme utilizes a vector matrix product logic, which performs a number of floating-point multiplications, additions, and accumulations. The logic is verified, synthesized, and shown to fit in the area resource available for the X-ray detector under study, which comprises 192 x 168 pixels each of 12-bit width, and having a total area of 20 mm x 20 mm, about 2 mm x 20 mm of which are available for the digital logic. Several system architectures, precisions, and compression ratios ranging from 100 to 250 were analyzed to pave the way for on-chip fixed-length compression (e.g., principal component analysis, singular value decomposition) and data reduction (e.g., azimuthal integration) for X-ray and electron detectors.