Architecture and FPGA Implementation of Digital Time-to-Digital Converter for Sensing Applications

TL;DR

This paper presents a FPGA-based digital time-to-digital converter (DTDC) design using multiple delay line topologies, achieving high precision and low resource utilization for sensing applications.

Contribution

It introduces a novel FPGA implementation of a DTDC with multiple delay line topologies, optimized for low power and resource efficiency.

Findings

Effective period conversion up to 1ps

Resource utilization less than 1% on FPGA

Successful FPGA implementation and simulation results

Abstract

Many application domains face the challenges of high-power consumption and high computational demands, especially with the advancement in embedded machine learning and edge computing. Designing application-specific circuits is crucial to reducing hardware complexity and power consumption. In these perspectives, this paper presents the design of a Digital Time-to-Digital converter (DTDC) based on multiple delay line topologies. The DTDC is implemented in VHDL for the Xilinx Artix-7 AC701 FPGA device. Simulation results demonstrate the effectiveness of the circuit in converting the input period along a wide range up to 1ps. The designed circuit is implemented with less than 1% of the resource utilization on the target FPGA device.