Designing with Deception: ML- and Covert Gate-Enhanced Camouflaging to Thwart IC Reverse Engineering
Junling Fan, David Koblah, Domenic Forte

TL;DR
This paper introduces a machine learning-based IC camouflage method that employs novel deception techniques and covert gates to effectively protect against reverse engineering attacks, maintaining functionality and appearance while resisting AI-driven threats.
Contribution
It presents a new ML-driven approach using AIG-VAE for dual-layered camouflage and introduces covert gates for enhanced hardware security, bridging a gap in mimetic deception strategies.
Findings
High camouflage and similarity scores achieved
Maintains circuit functionality with minimal overhead
Proven robustness against AI-enhanced reverse engineering attacks
Abstract
Integrated circuits (ICs) are essential to modern electronic systems, yet they face significant risks from physical reverse engineering (RE) attacks that compromise intellectual property (IP) and overall system security. While IC camouflage techniques have emerged to mitigate these risks, existing approaches largely focus on localized gate modifications, neglecting comprehensive deception strategies. To address this gap, we present a machine learning (ML)-driven methodology that integrates cryptic and mimetic cyber deception principles to enhance IC security against RE. Our approach leverages a novel And-Inverter Graph Variational Autoencoder (AIG-VAE) to encode circuit representations, enabling dual-layered camouflage through functional preservation and appearance mimicry. By introducing new variants of covert gates -- Fake Inverters, Fake Buffers, and Universal Transmitters -- our…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · Cryptographic Implementations and Security · Adversarial Robustness in Machine Learning
