Hardware-friendly IR-HARQ for Polar SCL Decoders

TL;DR

This paper proposes a hardware-efficient IR-HARQ scheme for polar SCL decoders by transforming set-based operations into binary vector operations and introducing a fast node integration approach, reducing area overhead.

Contribution

It introduces a novel hardware-friendly IR-HARQ scheme for polar decoders that minimizes area overhead by transforming operations and optimizing fast node integration.

Findings

Memory overhead of 25-27% compared to SCL decoding without IR-HARQ

Transforms set-based operations into binary vector operations

Introduces a fast node integration approach that reduces area overhead

Abstract

To extend the applications of polar codes within next-generation wireless communication systems, it is essential to incorporate support for Incremental Redundancy (IR) Hybrid Automatic Repeat Request (HARQ) schemes. The baseline IR-HARQ scheme's reliance on set-based operations leads to irregular memory access patterns, posing significant challenges for efficient hardware implementation. Furthermore, the introduction of new bit types increases the number of fast nodes that are decoded without traversing the sub-tree, resulting in a substantial area overhead when implemented in hardware. To address these issues and improve hardware compatibility, we propose transforming the set-based operations within the polar IR-HARQ scheme into binary vector operations. Additionally, we introduce a new fast node integration approach that avoids increasing the number of fast nodes, thereby minimizing the associated area overhead. Our proposed scheme results in a memory overhead of 25-27% compared to successive cancellation list (SCL) decoding without IR-HARQ support.