ARISE: Automating RISC-V Instruction Set Extension

TL;DR

ARISE automates RISC-V instruction set extension generation, optimizing code size and instruction count reduction through a flexible, metric-driven approach that integrates with existing tools.

Contribution

It introduces ARISE, a tool that automates RISC-V instruction set extensions using assembly patterns and metrics, streamlining optimization and integration.

Findings

Static code size reduced by 1.48%

Dynamic code size reduced by 3.84%

Instruction count decreased by 7.39% on average

Abstract

RISC-V is an extendable Instruction Set Architecture, growing in popularity for embedded systems. However, optimizing it to specific requirements, imposes a great deal of manual effort. To bridge the gap between software and ISA, the tool ARISE is presented. It automates the generation of RISC-V instructions based on assembly patterns, which are selected by an extendable set of metrics. These metrics implement the optimization goals of code size and instruction count reduction, both statically and dynamically. The instruction set extensions are generated using the ISA description language CoreDSL. Allowing seamless embedding in advanced tools such as the retargeting compiler Seal5 or the instruction set simulator ETISS. ARISE improves the static code size by 1.48% and the dynamic code size by 3.84%, as well as the number of instructions to be executed by 7.39% on average for Embench-Iot.