Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes

TL;DR

This paper explores a wire-efficient, high-density domain-specific processor architecture optimized for advanced nodes, demonstrating significant reductions in wire length and increases in density with minimal manual layout effort.

Contribution

It introduces a novel DSIP architecture optimized for wire efficiency and high density, validated through synthesis on the IMEC A10 node, outperforming the state-of-the-art baseline.

Findings

Over 2x lower normalized wire length compared to baseline

More than 3x higher density than the state-of-the-art

Low variability in physical design metrics across configurations

Abstract

This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect efficiency in advanced Angstrom-era technologies. The design emphasizes reduced wire length and high core density by utilizing specialized memory structures and SIMD (Single Instruction, Multiple Data) units. Five configurations are synthesized and evaluated using the IMEC A10 nanosheet node PDK. Key physical design metrics are compared across configurations and against VWR2A, a state-of-the-art (SoA) DSIP baseline. Results show that our architecture achieves over 2x lower normalized wire length and more than 3x higher density than the SoA, with low variability in the metrics across all configurations, making it a promising solution for next-generation DSIP designs. These improvements are achieved with minimal manual layout intervention, demonstrating the architecture's intrinsic physical efficiency and potential for low-cost wire-friendly implementation.